公开(公告)号：US20110254092A1

公开(公告)日：2011-10-20

申请号：US12759969

申请日：2010-04-14

Applicant: Bin Yang ,  Michael Hargrove

Inventor： Bin Yang ,  Michael Hargrove

IPC: H01L27/092 ,  H01L21/31

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/12 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/78654

Abstract: A semiconductor is formed on an ETSOI layer, the thin Si layer of an ETSOI substrate, with enhanced channel stress. Embodiments include semiconductor devices having dual stress liners on the back surface of the ETSOI layer. An embodiment includes forming an ETSOI substrate comprising an extra thin layer of Si on a backside substrate with an insulating layer, e.g., a BOX, there between, forming a semiconductor device on the Si surface, removing the backside substrate, as by CMP and the insulting layer, as by wet etching, and forming a stress liner on the backside of the remaining Si layer opposite the semiconductor device. The use of stress liners on the backside of the ETSOI layer enhances channel stress without modifying ETSOI semiconductor process flow.

Abstract translation: 在ETSOI层，ETSOI衬底的薄Si层上形成半导体，具有增强的沟道应力。 实施例包括在ETSOI层的背面上具有双重应力衬垫的半导体器件。 一个实施例包括在背面基板上形成包括超薄Si层的ETSOI衬底，其上具有诸如BOX之间的绝缘层（例如BOX），在Si表面上形成半导体器件，通过CMP和 绝缘层，如通过湿蚀刻，并且在与半导体器件相对的剩余Si层的背面上形成应力衬垫。 在ETSOI层的背面使用应力衬垫增强了通道应力，而不改变ETSOI半导体工艺流程。

公开(公告)号：US08294211B2

公开(公告)日：2012-10-23

申请号：US12687610

申请日：2010-01-14

Applicant: Bin Yang ,  Rohit Pal ,  Michael Hargrove

Inventor： Bin Yang ,  Rohit Pal ,  Michael Hargrove

IPC: H01L29/786

CPC classification number: H01L27/12 ,  H01L21/84 ,  H01L21/845 ,  H01L23/485 ,  H01L27/1211

Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

Abstract translation: 此处提供制造具有背面导电插头的半导体器件的方法。 该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。 栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。 该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。 接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

公开(公告)号：US08373228B2

公开(公告)日：2013-02-12

申请号：US12687607

申请日：2010-01-14

Applicant: Bin Yang ,  Rohit Pal ,  Michael Hargrove

Inventor： Bin Yang ,  Rohit Pal ,  Michael Hargrove

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L21/845 ,  H01L23/485 ,  H01L27/12 ,  H01L27/1211

Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

Abstract translation: 此处提供制造具有背面导电插头的半导体器件的方法。 该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。 栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。 该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。 接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

公开(公告)号：US20180104815A1

公开(公告)日：2018-04-19

申请号：US15686822

申请日：2017-08-25

Applicant: Bin Yang

Inventor： Bin Yang

IPC: B25J9/08 ,  B25J11/00 ,  B25J19/02

CPC classification number: B25J9/08 ,  B25J9/1617 ,  B25J9/162 ,  B25J11/0085 ,  B25J19/005 ,  B25J19/023 ,  G05B2219/31094 ,  G05B2219/40302 ,  G05B2219/40304 ,  Y02P90/18 ,  Y10S901/01

Abstract: A robot system includes a primary robot frame including a computerized control module providing control commands for the robot system, the primary robot frame including an outer perimeter. The robot system further includes a plurality of submodules, each submodule capable of being selectively docked with the primary robot frame, the submodules each providing different functionality to the robot system. The submodules, when docked with the primary robot frame, fit within the outer perimeter, enabling the robot system to operate in a closed mode, wherein all movement of the robot system is based upon the outer perimeter.

公开(公告)号：US09127088B2

公开(公告)日：2015-09-08

申请号：US13697018

申请日：2011-05-10

Applicant: Richard D. DiMarchi ,  Bin Yang ,  Brian Finan

Inventor： Richard D. DiMarchi ,  Bin Yang ,  Brian Finan

IPC: A61K38/26 ,  C07K14/62 ,  C07K14/72 ,  A61K47/48 ,  C07K14/605

CPC classification number: C07K14/721 ,  A61K38/26 ,  A61K47/55 ,  A61K47/554 ,  A61K47/64 ,  C07K14/605 ,  C07K14/72

Abstract: Provided herein are glucagon superfamily peptides conjugated with NHR ligands that are capable of acting at a nuclear hormone receptor. Also provided herein are pharmaceutical compositions and kits of the conjugates of the invention. Further provided herein are methods of treating a disease, e.g., a metabolic disorder, such as diabetes and obesity, comprising administering the conjugates of the invention.

Abstract translation: 本文提供了与能够作用于核激素受体的NHR配体缀合的胰高血糖素超家族肽。 本文还提供了本发明的缀合物的药物组合物和试剂盒。 本文还提供了治疗疾病，例如代谢紊乱（例如糖尿病和肥胖症）的方法，其包括施用本发明的缀合物。

公开(公告)号：US09111341B2

公开(公告)日：2015-08-18

申请号：US13997258

申请日：2011-12-23

Applicant: Gaoyang Wang ,  Wenfa Qi ,  Lidong Wang ,  Bin Yang

Inventor： Gaoyang Wang ,  Wenfa Qi ,  Lidong Wang ,  Bin Yang

IPC: G06K9/00 ,  G06T1/00 ,  G06K9/34

CPC classification number: G06T1/0021 ,  G06K9/348 ,  G06K2209/01 ,  G06T2201/0051 ,  G06T2201/0062 ,  G06T2201/0083

Abstract: The application provides a method for partitioning a watermark image with western language characters, comprising: partitioning a western language characters image along rows and columns to form a plurality of character image blocks; identifying valid character image blocks from the formed character image blocks; counting sizes of the valid character image blocks to determine if the image corresponds to a document with a large font size or a document with a small font size; dividing words in the image into a plurality of groups, wherein each divided group in the document with large font size has different numbers of words from that with small font size; and dividing equally the divided word groups into multiple portions corresponding to watermark image blocks. The application further provides a device for partitioning a watermark image with western language characters. The operability of watermark embedding process can be ensured through the above technical solution.

Abstract translation: 该应用程序提供了一种用于用西方语言字符分割水印图像的方法，包括：沿着行和列划分西方语言字符图像以形成多个字符图像块; 从形成的字符图像块中识别有效的字符图像块; 计算有效字符图像块的大小，以确定图像是否对应于具有较大字体大小的文档或具有小字体大小的文档; 将图像中的单词划分成多个组，其中具有大字体大小的文档中的每个划分组具有与具有小字体尺寸的单词不同的字数; 并将划分的字组分成相当于水印图像块的多个部分。 该应用还提供了一种用于用西语字符分割水印图像的设备。 通过上述技术方案可以确保水印嵌入过程的可操作性。

公开(公告)号：US08980830B2

公开(公告)日：2015-03-17

申请号：US12740206

申请日：2008-10-27

Applicant: Richard D. Dimarchi ,  Bin Yang ,  Chenguang Ouyang

Inventor： Richard D. Dimarchi ,  Bin Yang ,  Chenguang Ouyang

IPC: C07K14/605 ,  C07K7/02 ,  A61K38/26 ,  A61K38/16 ,  A61K38/22 ,  A61P3/04 ,  A61P3/10 ,  A61K38/00

CPC classification number: C07K14/605 ,  A61K38/00 ,  A61K38/16 ,  A61K38/22 ,  A61K38/26 ,  C07K7/02

Abstract: Glucagon analogs are disclosed that exhibit both glucagon antagonist and GLP-1 agonist activity. In one embodiment, the glucagon antagonist/GLP-1 agonist comprises a modified amino acid sequence of native glucagon, in which the first one to five N-terminal amino acids of native glucagon is deleted and in which the alpha helix is stabilized.

Abstract translation: 公开了显示胰高血糖素拮抗剂和GLP-1激动剂活性的胰高血糖素类似物。 在一个实施方案中，胰高血糖素拮抗剂/ GLP-1激动剂包含天然胰高血糖素的修饰的氨基酸序列，其中天然胰高血糖素的前一至五个N-末端氨基酸被缺失，并且其中α螺旋被稳定。

公开(公告)号：US20140055152A1

公开(公告)日：2014-02-27

申请号：US13594292

申请日：2012-08-24

Applicant: Amol Joshi ,  Charlene Chen ,  John Foster ,  Zhendong Hong ,  Olov Karlsson ,  Bei Li ,  Dipankar Pramanik ,  Usha Raghuram ,  Mark Victor Raymond ,  Jingang Su ,  Bin Yang

Inventor： Amol Joshi ,  Charlene Chen ,  John Foster ,  Zhendong Hong ,  Olov Karlsson ,  Bei Li ,  Dipankar Pramanik ,  Usha Raghuram ,  Mark Victor Raymond ,  Jingang Su ,  Bin Yang

IPC: G01R27/08

CPC classification number: G01R27/08 ,  G01R31/2831 ,  H01L22/14 ,  H01L22/20

Abstract: Methods and structures are described for determining contact resistivities and Schottky barrier heights for conductors deposited on semiconductor wafers that can be combined with combinatorial processing, allowing thereby numerous processing conditions and materials to be tested concurrently. Methods for using multi-ring as well as single-ring CTLM structures to cancel parasitic resistance are also described, as well as structures and processes for inline monitoring of properties.

Abstract translation: 描述了用于确定沉积在可与组合处理组合的半导体晶片上的导体的接触电阻率和肖特基势垒高度的方法和结构，从而允许同时测试许多处理条件和材料。 还描述了使用多环以及单环CTLM结构来消除寄生电阻的方法，以及用于在线监测性质的结构和方法。

公开(公告)号：US20140033937A1

公开(公告)日：2014-02-06

申请号：US13996967

申请日：2011-12-24

Applicant: Haifeng Li ,  Bin Yang

Inventor： Haifeng Li ,  Bin Yang

IPC: G03F5/20

CPC classification number: G03F5/20 ,  H04N1/4055

Abstract: The present application provides a screen method for intaglio printing, comprising: dividing multiple classes of regions according to a brightness range; and generating screen dots with various screen patterns for the grouped classes of regions. The present application also provides a screen device for intaglio printing, comprising: a dividing module configured to group multiple classes of regions according to the brightness range; and a generating module configured to generate screen dots with various screen patterns for the grouped classes of regions. Since multiple kinds of screen patterns are applied in the technical solutions in present application, the problem, i.e., water ripple will occur in the prior art, may be addressed, so as to improve the quality of printing.

Abstract translation: 本申请提供了一种用于凹版印刷的屏幕方法，包括：根据亮度范围划分多个类别的区域; 并且为分组的区域类别生成具有各种屏幕图案的屏幕点。 本申请还提供了一种用于凹版印刷的屏幕装置，包括：分割模块，被配置为根据亮度范围对多个类别的区域进行分组; 以及生成模块，被配置为生成用于所述分组的区域类别的各种屏幕图案的屏幕点。 由于在本申请中的技术方案中应用了多种屏幕图案，所以可以解决现有技术中出现的水波纹问题，以提高打印质量。

公开(公告)号：US08497308B2

公开(公告)日：2013-07-30

申请号：US12439872

申请日：2007-09-05

Applicant: Anna Lee Y. Tonkovich ,  Robert D. Litt ,  Timothy M. Werner ,  Bin Yang

Inventor： Anna Lee Y. Tonkovich ,  Robert D. Litt ,  Timothy M. Werner ,  Bin Yang

IPC: C07C27/00

CPC classification number: B01J19/0093 ,  B01J19/1831 ,  B01J2219/00783 ,  B01J2219/00835 ,  B01J2219/00873 ,  B01J2219/00984 ,  C07C29/152 ,  C10G2/341 ,  C07C31/04

Abstract: A process for carrying out at least two unit operations in series, the process comprising the step of: (a) directing a feed stream into an integrated assembly which comprises a first microchannel unit operation upon at least one chemical of the feed stream to generate a distributed output stream that exits the first microchannel unit operation in a first set of discrete microchannels isolating flow through the discrete microchannels; and (b) directing the distributed output stream of the first microchannel unit operation into a second microchannel unit operation as a distributed input stream, to continue isolating flow between the first set of discrete microchannels, and conducting at least one operation upon at least one chemical of the input stream to generate a product stream that exits the second microchannel unit operation, where the first microchannel unit operation and the second unit operation share a housing.

Abstract translation: 一种用于串联进行至少两个单元操作的方法，该方法包括以下步骤：（a）将进料流引导到集成组件中，其包括在进料流的至少一种化学品上的第一微通道单元操作以产生 在第一组离散微通道中离开第一微通道单元操作的分布式输出流，其隔离通过离散微通道的流动; 和（b）将第一微通道单元操作的分布式输出流引导到作为分布式输入流的第二微通道单元操作中，以继续隔离第一组离散微通道之间的流动，并且至少一种化学物质进行至少一种操作 以产生离开第二微通道单元操作的产品流，其中第一微通道单元操作和第二单元操作共享外壳。