公开(公告)号：US06281559B1

公开(公告)日：2001-08-28

申请号：US09261274

申请日：1999-03-03

Applicant: Bin Yu ,  Ercan Adem

Inventor： Bin Yu ,  Ercan Adem

IPC: H01L31119

CPC classification number: H01L21/82345 ,  H01L21/2807 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/4966

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures or gate stacks with a silicon and germanium material provided over a seed layer. The seed layer can be a 20-40 Å polysilicon layer. An amorphous silicon layer is provided over the silicon and germanium material, and a cap layer is provided over the amorphous silicon layer. The polysilicon material is implanted with lower concentrations of germanium, where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV.

Abstract translation: 超大规模集成（ULSI）电路包括具有不同阈值电压但具有相同通道特性的MOSFET。 MOSFET包括在种子层上提供硅和锗材料的栅极结构或栅极堆叠。 种子层可以是20-40多晶硅层。 在硅和锗材料上提供非晶硅层，并且在非晶硅层上提供覆盖层。 用较低浓度的锗注入多晶硅材料，其中需要较低的阈值电压MOSFET。 在锗的0-60％浓度范围内，阈值电压可以改变大约240mV。

公开(公告)号：US06667070B1

公开(公告)日：2003-12-23

申请号：US10061349

申请日：2002-02-04

Applicant: Ercan Adem

Inventor： Ercan Adem

IPC: C23C1652

CPC classification number: C23C16/52

Abstract: A novel method is provided for in situ monitoring of a film being deposited on a wafer for manufacturing a semiconductor device. The method involves producing an incident beam of radiation directed during a deposition process to a film being deposited on a wafer in a deposition reactor. The Raman scattered radiation resulted from interaction of the incident beam with molecules of the deposited film is detected to produce a Raman spectrum of the deposited film.

Abstract translation: 提供一种新颖的方法用于原位监测沉积在用于制造半导体器件的晶片上的膜。 该方法包括在沉积过程中将沉积在晶片上的膜的沉积反应器中产生的辐射入射光束产生。 检测入射光束与沉积膜分子相互作用产生的拉曼散射辐射，产生沉积膜的拉曼光谱。

公开(公告)号：US20070020919A1

公开(公告)日：2007-01-25

申请号：US11173244

申请日：2005-07-01

Applicant: Ercan Adem ,  Nicholas Tripsas

Inventor： Ercan Adem ,  Nicholas Tripsas

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76849 ,  H01L21/76834 ,  H01L21/76886

Abstract: Methods are described for eliminating void formation during the fabrication of and/or operation of memory cells/devices. According to one aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the opening, preamorphization of the metal using preamorphization implants, and formation of a conductivity facilitating layer. According to another aspect of the present disclosure, the methods to eliminate voids include formation of an opening on a semiconductor structure, formation of a diffusion barrier layer, deposition of a metal into the opening, preamorphization of the metal using a contact with a plasma, and formation of a conductivity facilitating layer.

Abstract translation: 描述了在存储器单元/器件的制造和/或操作期间消除空隙形成的方法。 根据本公开的一个方面，消除空隙的方法包括在半导体结构上形成开口，形成扩散阻挡层，将金属沉积到开口中，使用预变形植入物预先形成金属，以及形成 导电促进层。 根据本公开的另一方面，消除空隙的方法包括在半导体结构上形成开口，形成扩散阻挡层，将金属沉积到开口中，使用与等离子体接触进行金属预变质， 并形成导电促进层。

公开(公告)号：US06562718B1

公开(公告)日：2003-05-13

申请号：US09729700

申请日：2000-12-06

Applicant: Qi Xiang ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  George J. Kluth ,  Minh V. Ngo ,  Eric N. Paton ,  Christy Mei-Chu Woo

Inventor： Qi Xiang ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John C. Foster ,  Paul L. King ,  George J. Kluth ,  Minh V. Ngo ,  Eric N. Paton ,  Christy Mei-Chu Woo

IPC: H01L2144

CPC classification number: H01L29/66507 ,  H01L21/28097

Abstract: A method of forming a fully silicidized gate of a semiconductor device includes forming silicide in active regions and a portion of a gate. A shield layer is blanket deposited over the device. The top surface of the gate electrode is then exposed. A refractory metal layer is deposited and annealing is performed to cause the metal to react with the gate and fully silicidize the gate, with the shield layer protecting the active regions of the device from further silicidization to thereby prevent spiking and current leakage in the active regions.

Abstract translation: 形成半导体器件的完全硅化栅极的方法包括在有源区和门的一部分中形成硅化物。 屏蔽层被覆盖在该器件上。 然后露出栅电极的顶表面。 沉积难熔金属层并进行退火以使金属与栅极反应并使栅极完全硅化，屏蔽层保护器件的有源区不受另外的硅化，从而防止有源区中的峰值和电流泄漏 。

公开(公告)号：US06518185B1

公开(公告)日：2003-02-11

申请号：US10127521

申请日：2002-04-22

Applicant: Pin-Chin Connie Wang ,  Fei Wang ,  Kashmir Sahota ,  Steven Avanzino ,  Amit Marathe ,  Matthew Buynoski ,  Ercan Adem ,  Christy Woo

Inventor： Pin-Chin Connie Wang ,  Fei Wang ,  Kashmir Sahota ,  Steven Avanzino ,  Amit Marathe ,  Matthew Buynoski ,  Ercan Adem ,  Christy Woo

IPC: H01L2144

CPC classification number: H01L21/76877

Abstract: In the present method of fabricating a semiconductor device, openings of different configurations (for example, different aspect ratios) are provided in a dielectric layer. Substantially undoped copper is deposited over the dielectric layer, filling the openings and extending above the dielectric layer, the different configurations of the openings providing an upper surface of the substantially undoped copper that is generally non-planar. A portion of the substantially undoped copper is removed to provide a substantially planar upper surface thereof, and a layer of doped copper is deposited on the upper surface of the substantially undoped copper. An anneal step is undertaken to difffuse the doping element into the copper in the openings.

Abstract translation: 在本发明的半导体装置的制造方法中，在介质层中设置不同结构（例如不同的纵横比）的开口。 基本上未掺杂的铜沉积在电介质层上，填充开口并在电介质层上方延伸，开口的不同构型提供通常为非平面的基本未掺杂的铜的上表面。 去除基本上未掺杂的铜的一部分以提供其基本平坦的上表面，并且在基本未掺杂的铜的上表面上沉积掺杂的铜层。 进行退火步骤以将掺杂元素扩散到开口中的铜中。

公开(公告)号：US06605513B2

公开(公告)日：2003-08-12

申请号：US09729699

申请日：2000-12-06

Applicant: Eric N. Paton ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  George Jonathan Kluth ,  Minh Van Ngo ,  Christy Mei-Chu Woo

Inventor： Eric N. Paton ,  Ercan Adem ,  Jacques J. Bertrand ,  Paul R. Besser ,  Matthew S. Buynoski ,  John Clayton Foster ,  Paul L. King ,  George Jonathan Kluth ,  Minh Van Ngo ,  Christy Mei-Chu Woo

IPC: H01L21336

CPC classification number: H01L29/665 ,  H01L21/28061 ,  H01L21/28518 ,  H01L29/4933

Abstract: A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy is reacted with a silicon material to form at least one high resistance nickel silicide region. Unreacted nickel is removed. A dielectric layer is then deposited over a high resistance nickel silicide regions. In a second temperature treatment, the at least one high resistance nickel silicide region and dielectric layer are reacted at a prescribed temperature to form at least one low resistance silicide region and process the dielectric layer. Bridging between regions is avoided by the two-step process as silicide growth is controlled, and unreacted nickel between silicide regions is removed after the first temperature treatment. The processing of the high resistance nickel silicide regions and the dielectric layer are conveniently combined into a single temperature treatment.

Abstract translation: 自对准硅化物工艺，可以适应低热预算，并在受控反应中形成小尺寸的硅化物区域。 在第一温度处理中，镍金属或镍合金与硅材料反应以形成至少一个高电阻镍硅化物区域。 去除未反应的镍。 然后将电介质层沉积在高电阻镍硅化物区域上。 在第二温度处理中，至少一个高电阻镍硅化物区域和电介质层在规定温度下反应以形成至少一个低电阻硅化物区域并处理介电层。 通过控制硅化物生长的两步法避免区域之间的桥接，并且在第一温度处理之后去除硅化物区域之间的未反应的镍。 将高电阻镍硅化物区域和电介质层的处理方便地组合成单温度处理。

公开(公告)号：US06521529B1

公开(公告)日：2003-02-18

申请号：US09679880

申请日：2000-10-05

Applicant: Minh Van Ngo ,  Christy Mei-Chu Woo ,  Ercan Adem ,  Robert A. Huertas

Inventor： Minh Van Ngo ,  Christy Mei-Chu Woo ,  Ercan Adem ,  Robert A. Huertas

IPC: H01L2144

CPC classification number: H01L29/665 ,  H01L21/28518 ,  H01L29/6656 ,  Y10S257/90

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented, after silicidation and removal of any unreacted nickel, by treating the exposed surfaces of the silicon nitride sidewall spacers with a HDP plasma to oxidize nickel silicide thereon forming a surface layer comprising silicoin oxide and silicon oxynitride. Embodiments include treating the silicon nitride sidewall spacers with a HDP plasma to form a surface silicon oxide/silicon oxynitride region having a thickness of about 40 Å to about 50 Å.

Abstract translation: 通过用HDP等离子体处理氮化硅侧壁间隔物的暴露表面以氧化硅化镍，在硅化和除去任何未反应的镍之后，阻止栅电极上的硅化镍层与氮化硅侧壁间隔物的源/漏区之间的桥接 其上形成包含硅氧烷氧化物和氮氧化硅的表面层。 实施例包括用HDP等离子体处理氮化硅侧壁间隔物以形成厚度为大约至大约的表面氧化硅/氧氮化硅区域。

公开(公告)号：US06869878B1

公开(公告)日：2005-03-22

申请号：US10367406

申请日：2003-02-14

Applicant: Ercan Adem ,  John E. Sanchez ,  Darrell M. Erb ,  Suzette K. Pangrle

Inventor： Ercan Adem ,  John E. Sanchez ,  Darrell M. Erb ,  Suzette K. Pangrle

IPC: H01L21/44 ,  H01L21/4763 ,  H01L21/768

CPC classification number: H01L21/76849 ,  H01L21/76807 ,  H01L21/76885

Abstract: The reliability and performance of planarized metallization patterns in an electrical device, for example copper, inlaid in the surface of a layer of dielectric material overlying a semiconductor wafer substrate, are enhanced by a method for reliably depositing a barrier layer selective to the metallization patterns. The method comprises forming a sacrificial dielectric layer above a substrate. Metallization patterns are formed in the sacrificial dielectric layer. The barrier layer is selectively deposited on the metallization patterns. Portions of the barrier material undesirably deposited on the sacrificial dielectric layer are removed by removing the sacrificial dielectric layer, thus preventing bridging of adjacent metallization features by the barrier layer portions. An interlevel dielectric layer is then formed in place of the sacrificial dielectric layer. The selectively deposited barrier layer advantageously reduces parasitic capacitance between metallization features in comparison to a conventional blanket-deposited silicon nitride barrier layer.

Abstract translation: 通过用于可靠地沉积对金属化图案有选择性的阻挡层的方法，增强了嵌入在覆盖在半导体晶片衬底上的介电材料层的表面中的电子器件（例如铜）中的平面化金属化图案的可靠性和性能。 该方法包括在衬底上形成牺牲介电层。 在牺牲电介质层中形成金属化图案。 阻挡层选择性地沉积在金属化图案上。 通过去除牺牲介电层来去除不期望地沉积在牺牲介电层上的阻挡材料的部分，从而防止相邻金属化特征由阻挡层部分桥接。 然后形成层间电介质层代替牺牲电介质层。 与常规的覆盖层沉积的氮化硅阻挡层相比，选择性沉积的势垒层有利地减小了金属化特征之间的寄生电容。

公开(公告)号：US06641747B1

公开(公告)日：2003-11-04

申请号：US09783204

申请日：2001-02-15

Applicant: Todd P. Lukanc ,  Ercan Adem

Inventor： Todd P. Lukanc ,  Ercan Adem

IPC: C23C1600

CPC classification number: H01J37/32935 ,  H01J37/32963

Abstract: An apparatus and method for detecting an endpoint for an etching process utilize a reaction chamber with an ion source and detector placed within the reaction chamber. The ion source directs a primary beam of ions towards a wafer so that the ion beam impacts the top layer of the wafer. A detector detects primary ions reflected from the wafer and secondary ions scattered from the wafer. A value is determined that corresponds to the amount of reflected and scattered ions. A change in the value indicates that the ion beam is impacting a layer beneath the top layer of the wafer, and signifies the reaching of the etch process endpoint.

Abstract translation: 用于检测蚀刻过程的端点的装置和方法利用具有放置在反应室内的离子源和检测器的反应室。 离子源将一次离子束照射到晶片，使得离子束撞击晶片的顶层。 检测器检测从晶片反射的一次离子和从晶片散射的二次离子。 确定对应于反射和散射离子的量的值。 值的变化表示离子束影响晶片顶层下方的层，并表示蚀刻工艺终点的到达。

公开(公告)号：US06583070B1

公开(公告)日：2003-06-24

申请号：US09778777

申请日：2001-02-08

Applicant: Ting Y. Tsui ,  Ercan Adem

Inventor： Ting Y. Tsui ,  Ercan Adem

IPC: H01L2131

CPC classification number: H01L23/5329 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

Abstract: A semiconductor device having a reduced resistance-capacitance time constant is formed by treating a dielectric layer to reduce its dielectric constant. Embodiments include exposing a deposited dielectric layer to ionic radiation, as with Helium ion implantation, to form voids within the layer, thereby reducing its dielectric constant.

Abstract translation: 通过处理电介质层以减小其介电常数，形成具有降低的电阻 - 电容时间常数的半导体器件。 实施例包括将沉积的介电层暴露于离子辐射，如同氦离子注入一样在层内形成空隙，由此降低其介电常数。