公开(公告)号：US20120235138A1

公开(公告)日：2012-09-20

申请号：US13481781

申请日：2012-05-26

申请人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Liu-Chung Lee

发明人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Liu-Chung Lee

IPC分类号： H01L29/12 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1225

摘要： A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.

摘要翻译： 制造具有减小的掩模操作的TFT和IPS的方法包括基板，栅极，栅极上的栅极电介质层和周围的衬底表面以及栅极电介质上的半导体金属氧化物。 沟道保护层覆盖栅极以限定半导体金属氧化物中的沟道区。 S / D金属层在通道保护层和暴露的半导体金属氧化物的一部分上被图案化以限定IPS区域。 在S / D端子和IPS区域的相对侧上构图有机电介质材料。 蚀刻S / D金属以暴露限定第一IPS电极的半导体金属氧化物。 钝化层覆盖第一电极，并且在钝化层上图案化透明导电材料层以限定覆盖第一电极的第二IPS电极。

公开(公告)号：US09129868B2

公开(公告)日：2015-09-08

申请号：US13481781

申请日：2012-05-26

申请人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Liu-Chung Lee

发明人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Liu-Chung Lee

IPC分类号： H01L21/00 ,  H01L27/12

CPC分类号： H01L27/1288 ,  H01L27/1225

摘要： A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.

摘要翻译： 制造具有减小的掩模操作的TFT和IPS的方法包括基板，栅极，栅极上的栅极电介质层和周围的衬底表面以及栅极电介质上的半导体金属氧化物。 沟道保护层覆盖栅极以限定半导体金属氧化物中的沟道区。 S / D金属层在通道保护层和暴露的半导体金属氧化物的一部分上被图案化以限定IPS区域。 在S / D端子和IPS区域的相对侧上构图有机电介质材料。 蚀刻S / D金属以暴露限定第一IPS电极的半导体金属氧化物。 钝化层覆盖第一电极，并且在钝化层上图案化透明导电材料层以限定覆盖第一电极的第二IPS电极。

公开(公告)号：US09768322B2

公开(公告)日：2017-09-19

申请号：US15225592

申请日：2016-08-01

申请人： Gang Yu ,  Chan-Long Shieh ,  Tian Xiao ,  Fatt Foong

发明人： Gang Yu ,  Chan-Long Shieh ,  Tian Xiao ,  Fatt Foong

IPC分类号： H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L23/00 ,  H01L21/8234 ,  H01L21/4763 ,  H01L21/324 ,  H01L21/321 ,  H01L21/383 ,  H01L21/477 ,  H01L21/428 ,  H01L29/45 ,  H01L21/44 ,  H01L23/31

CPC分类号： H01L29/7869 ,  H01L21/321 ,  H01L21/324 ,  H01L21/383 ,  H01L21/428 ,  H01L21/44 ,  H01L21/47635 ,  H01L21/477 ,  H01L21/823418 ,  H01L23/3171 ,  H01L23/564 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.

公开(公告)号：US20150357480A1

公开(公告)日：2015-12-10

申请号：US14829812

申请日：2015-08-19

申请人： Gang Yu ,  Chan-Long Shieh ,  Tian Xiao ,  Fatt Foong ,  Juergen Musulf ,  Karl Birger Kristoffer Ottosson

发明人： Gang Yu ,  Chan-Long Shieh ,  Tian Xiao ,  Fatt Foong ,  Juergen Musulf ,  Karl Birger Kristoffer Ottosson

IPC分类号： H01L29/786 ,  H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L21/283 ,  H01L21/324

CPC分类号： H01L29/78693 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02592 ,  H01L21/324 ,  H01L29/42364 ,  H01L29/7869 ,  H01L51/052

摘要： A thin film semiconductor device has a semiconductor layer including a composite/blend/mixture of an amorphous/nanocrystalline semiconductor ionic metal oxide and an amorphous/nanocrystalline non-semiconducting covalent metal oxide. A pair of terminals is positioned in communication with the semiconductor layer and define a semiconductive channel, and agate terminal is positioned in communication with the semiconductive channel and further positioned to control conduction of the channel. The invention further includes a method of depositing the mixture including using nitrogen during the deposition process to control the carrier concentration in the resulting semiconductor layer.

摘要翻译： 薄膜半导体器件具有包括非晶/纳米晶体半导体离子金属氧化物和非晶/纳米晶体非半导体共价金属氧化物的复合/共混物/混合物的半导体层。 一对端子定位成与半导体层连通并且限定半导体通道，并且玛瑙端子被定位成与半导体沟道连通并进一步定位成控制沟道的传导。 本发明还包括在沉积过程中沉积包括使用氮气的混合物的方法，以控制所得半导体层中的载流子浓度。

公开(公告)号：US20140346495A1

公开(公告)日：2014-11-27

申请号：US13902514

申请日：2013-05-24

申请人： Chan- Long Shieh ,  Gang Yu ,  Fatt Foong ,  Juergen Musolf

发明人： Chan- Long Shieh ,  Gang Yu ,  Fatt Foong ,  Juergen Musolf

IPC分类号： H01L29/786 ,  H01L29/66

CPC分类号： H01L29/66969 ,  H01L21/02063 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L27/1225 ,  H01L29/247 ,  H01L29/42384 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2021/775

摘要： A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer positioned over the gate. A carrier transport structure is deposited by sputtering on the gate dielectric layer. The carrier transport structure includes a layer of amorphous high mobility metal oxide adjacent the gate dielectric and a relatively inert protective layer of material deposited on the layer of amorphous high mobility metal oxide both deposited without oxygen and in situ. The layer of amorphous metal oxide has a mobility above 40 cm2/Vs and a carrier concentration in a range of approximately 1018 cm−3 to approximately 5×1019 cm−3. Source/drain contacts are positioned on the protective layer and in electrical contact therewith.

摘要翻译： 制造稳定的高迁移率无定形MOTFT的方法包括提供其上形成有栅极的基板和位于栅极上方的栅介质层的步骤。 通过溅射将载流子传输结构沉积在栅极介电层上。 载流子传输结构包括邻近栅极电介质的非晶高迁移率金属氧化物层，以及沉积在无氧和原位沉积的无定形高迁移率金属氧化物层上的相对惰性的材料保护层。 非晶金属氧化物层的迁移率高于40cm 2 / Vs，载流子浓度在约1018cm-3至约5×1019cm-3的范围内。 源极/漏极触点位于保护层上并与其电接触。

公开(公告)号：US20140001462A1

公开(公告)日：2014-01-02

申请号：US13536641

申请日：2012-06-28

申请人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Tian Xiao ,  Juergen Musolf

发明人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong ,  Tian Xiao ,  Juergen Musolf

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L29/7869 ,  H01L21/467 ,  H01L21/4763 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/78696

摘要： A method of fabricating a stable, high mobility metal oxide thin film transistor includes the steps of providing a substrate, positioning a gate on the substrate, and depositing a gate dielectric layer on the gate and portions of the substrate not covered by the gate. A multiple film active layer including a metal oxide semiconductor film and a metal oxide passivation film is deposited on the gate dielectric with the passivation film positioned in overlying relationship to the semiconductor film. An etch-stop layer is positioned on a surface of the passivation film and defines a channel area in the active layer. A portion of the multiple film active layer on opposite sides of the etch-stop layer is modified to form an ohmic contact and metal source/drain contacts are positioned on the modified portion of the multiple film active layer.

摘要翻译： 一种制造稳定的高迁移率金属氧化物薄膜晶体管的方法包括以下步骤：提供衬底，将栅极定位在衬底上，以及在栅极上沉积栅极电介质层，并且将衬底部分未被栅极覆盖。 包括金属氧化物半导体膜和金属氧化物钝化膜的多层膜活性层沉积在栅极电介质上，钝化膜位于与半导体膜的重叠关系中。 蚀刻停止层位于钝化膜的表面上并限定有源层中的沟道区。 在蚀刻停止层的相对侧上的多个膜有源层的一部分被修改以形成欧姆接触，并且金属源极/漏极触点位于多个膜有源层的修改部分上。

公开(公告)号：US08273600B2

公开(公告)日：2012-09-25

申请号：US13195882

申请日：2011-08-02

申请人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

发明人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

IPC分类号： H01L21/00

CPC分类号： H01L29/7869 ,  H01L21/02554 ,  H01L21/02565

摘要： A method of fabricating MOTFTs on transparent substrates by positioning opaque gate metal on the substrate front surface and depositing gate dielectric material overlying the gate metal and a surrounding area and metal oxide semiconductor material on the dielectric material. Depositing selectively removable etch stop material on the semiconductor material and photoresist on the etch stop material to define an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the substrate rear surface using the gate metal as a mask and removing exposed portions leaving the etch stop material overlying the gate metal covered. Etching the semiconductor material to isolate the TFT. Selectively etching the etch stop layer to leave a portion overlying the gate metal defining a channel area. Depositing and patterning conductive material to form source and drain areas on opposed sides of the channel area.

摘要翻译： 一种在透明基板上制造MOTFT的方法，该方法是将不透明栅极金属定位在衬底前表面上，并沉积覆盖在栅极金属上的栅介质材料以及介电材料上的周围区域和金属氧化物半导体材料。 在半导体材料和蚀刻停止材料上的光致抗蚀剂上沉积选择性可移除的蚀刻停止材料以限定半导体材料中的隔离区域。 去除蚀刻停止件的未覆盖部分。 使用栅极金属作为掩模从基板后表面露出光致抗蚀剂，并去除暴露部分，留下覆盖栅极金属的蚀刻停止材料。 蚀刻半导体材料以隔离TFT。 选择性地蚀刻蚀刻停止层以留下覆盖栅极金属的部分限定沟道区域。 沉积和图案化导电材料以在通道区域的相对侧上形成源区和漏区。

公开(公告)号：US20170033227A1

公开(公告)日：2017-02-02

申请号：US15225592

申请日：2016-08-01

申请人： Gang Yu ,  Chan-Long Shieh ,  Tian Xiao ,  Fatt Foong

发明人： Gang Yu ,  Chan-Long Shieh ,  Tian Xiao ,  Fatt Foong

IPC分类号： H01L29/786 ,  H01L23/00 ,  H01L23/31 ,  H01L29/49

CPC分类号： H01L29/7869 ,  H01L21/321 ,  H01L21/324 ,  H01L21/383 ,  H01L21/428 ,  H01L21/44 ,  H01L21/47635 ,  H01L21/477 ,  H01L21/823418 ,  H01L23/3171 ,  H01L23/564 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.

摘要翻译： 一种方法，包括提供具有栅极的衬底，与栅极相邻的栅极绝缘体材料层和位于与栅极相对的栅极绝缘体上的金属氧化物半导体材料层，形成选择性图案化的蚀刻停止钝化层并在高温下加热 在含氧或含氮或惰性气氛中选择性地增加未被蚀刻停止层覆盖的金属氧化物半导体的区域中的载流子浓度，其上形成有上层和间隔开的源极/漏极金属。 随后在含氧或含氮或惰性气氛中加热晶体管，以进一步改善源极/漏极接触，并将阈值电压调节到期望的水平。 在晶体管的顶部提供额外的钝化层，具有电气绝缘和对周围环境中的潮湿和化学物质的阻隔性能。

公开(公告)号：US09412623B2

公开(公告)日：2016-08-09

申请号：US14833462

申请日：2015-08-24

申请人： Gang Yu ,  Chan-Long Shieh ,  Tian Xiao ,  Fatt Foong

发明人： Gang Yu ,  Chan-Long Shieh ,  Tian Xiao ,  Fatt Foong

IPC分类号： H01L21/383 ,  H01L29/786 ,  H01L29/49 ,  H01L29/66 ,  H01L23/00 ,  H01L21/8234 ,  H01L21/4763 ,  H01L21/324 ,  H01L21/321 ,  H01L21/477 ,  H01L21/428 ,  H01L29/45

CPC分类号： H01L29/7869 ,  H01L21/321 ,  H01L21/324 ,  H01L21/383 ,  H01L21/428 ,  H01L21/44 ,  H01L21/47635 ,  H01L21/477 ,  H01L21/823418 ,  H01L23/3171 ,  H01L23/564 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material positioned on the gate insulator opposite the gate, forming a selectively patterned etch stop passivation layer and heating at elevated temperature in an oxygen-containing or nitrogen-containing or inert ambience to selectively increase the carrier concentration in regions of the metal oxide semiconductor not covered by the etch stop layer, on which overlying and spaced apart source/drain metals are formed. Subsequently heating the transistor in an oxygen-containing or nitrogen-containing or inert ambience to further improve the source/drain contacts and adjust the threshold voltage to a desired level. Providing additional passivation layer(s) on top of the transistor with electric insulation and barrier property to moisture and chemicals in the surrounding environment.

摘要翻译： 一种方法，包括提供具有栅极的衬底，与栅极相邻的栅极绝缘体材料层和位于与栅极相对的栅极绝缘体上的金属氧化物半导体材料层，形成选择性图案化的蚀刻停止钝化层并在高温下加热 在含氧或含氮或惰性气氛中选择性地增加未被蚀刻停止层覆盖的金属氧化物半导体的区域中的载流子浓度，其上形成有上层和间隔开的源极/漏极金属。 随后在含氧或含氮或惰性气氛中加热晶体管，以进一步改善源极/漏极接触并将阈值电压调节到所需的电平。 在晶体管的顶部提供额外的钝化层，具有电气绝缘和对周围环境中的潮湿和化学物质的阻隔性能。

公开(公告)号：US20160204278A1

公开(公告)日：2016-07-14

申请号：US15080231

申请日：2016-03-24

申请人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

发明人： Chan-Long Shieh ,  Gang Yu ,  Fatt Foong

IPC分类号： H01L29/786 ,  H01L27/12

CPC分类号： H01L29/78696 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

摘要： A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.

摘要翻译： 一种制造MO TFT的方法包括将不透明栅极金属定位在透明基板上以限定栅极区域。 覆盖栅极金属和周围区域的沉积栅介质材料，以及在其上沉积金属氧化物半导体材料。 在半导体材料上沉积蚀刻停止材料。 定义在半导体材料中限定隔离区域的光致抗蚀剂，蚀刻停止材料和光致抗蚀剂可选择性地移除。 从基板的后表面露出光致抗蚀剂，除去暴露的部分以使蚀刻停止材料未被覆盖，除了覆盖并与栅极金属对准的部分之外。 蚀刻半导体材料的未覆盖部分以隔离TFT。 使用光致抗蚀剂，选择性地蚀刻蚀刻停止层以留下覆盖并与栅极金属对准的部分并限定半导体材料中的沟道区域。 沉积和图案化导电材料以形成源区和漏区。