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公开(公告)号：US20100304530A1
公开(公告)日：2010-12-02
申请号：US12788956
申请日：2010-05-27
申请人： Choongbin Yim , Seungkon Mok , Donghan Kim , Jin-Woo Park , PaLan Lee , Mi-yeon Kim
发明人： Choongbin Yim , Seungkon Mok , Donghan Kim , Jin-Woo Park , PaLan Lee , Mi-yeon Kim
IPC分类号： H01L21/56
CPC分类号： H01L23/04 , H01L23/3128 , H01L25/105 , H01L2224/16225 , H01L2224/73204 , H01L2224/73253 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2224/0401
摘要： Provided is a method of forming a semiconductor package. In the method, a first package including a first chip on a first substrate is formed, a second package including a second chip on a second substrate is formed, a moulding cap provided with a via hole and a recess structure configured to receive the first chip is formed, and the second package is provided on the first package with the moulding cap being therebetween such that the recess receives the first chip. The via hole and the recess structure are simultaneously foamed.
摘要翻译： 提供一种形成半导体封装的方法。 在该方法中，形成包括在第一基板上的第一芯片的第一封装，在第二基板上形成包括第二芯片的第二封装，设置有通孔和凹陷结构的成型盖， 并且所述第二包装设置在所述第一包装上，所述模制帽在其间，使得所述凹部接收所述第一芯片。 通孔和凹槽结构同时发泡。
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公开(公告)号：US08569114B2
公开(公告)日：2013-10-29
申请号：US12788956
申请日：2010-05-27
申请人： Choongbin Yim , Seungkon Mok , Donghan Kim , Jin-Woo Park , PaLan Lee , Mi-yeon Kim
发明人： Choongbin Yim , Seungkon Mok , Donghan Kim , Jin-Woo Park , PaLan Lee , Mi-yeon Kim
IPC分类号： H01L21/00
CPC分类号： H01L23/04 , H01L23/3128 , H01L25/105 , H01L2224/16225 , H01L2224/73204 , H01L2224/73253 , H01L2225/1023 , H01L2225/1058 , H01L2924/00011 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2224/0401
摘要： Provided is a method of forming a semiconductor package. In the method, a first package including a first chip on a first substrate is formed, a second package including a second chip on a second substrate is formed, a molding cap provided with a via hole and a recess structure configured to receive the first chip is formed, and the second package is provided on the first package with the molding cap being therebetween such that the recess receives the first chip. The via hole and the recess structure are simultaneously formed.
摘要翻译： 提供一种形成半导体封装的方法。 在该方法中，形成包括在第一基板上的第一芯片的第一封装，在第二基板上形成包括第二芯片的第二封装，设置有通孔和凹陷结构的成型盖， 并且所述第二包装设置在所述第一包装上，所述模制帽在其间，使得所述凹部接收所述第一芯片。 通孔和凹槽结构同时形成。
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公开(公告)号：US20110018121A1
公开(公告)日：2011-01-27
申请号：US12805131
申请日：2010-07-14
申请人： Jinho Lee , Choongbin Yim , Jin-woo Park , Dae-young Choi , Mi-yeon Kim
发明人： Jinho Lee , Choongbin Yim , Jin-woo Park , Dae-young Choi , Mi-yeon Kim
CPC分类号： H01L21/76898 , H01L23/13 , H01L23/481 , H01L23/49822 , H01L23/49838 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/0557 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2924/00014 , H01L2924/0002 , H01L2924/01033 , H01L2924/014 , H01L2924/078 , H01L2924/09701 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second chip in the recessed portion, the second semiconductor chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via. A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second semiconductor chip in the recessed portion, the second chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via.
摘要翻译： 半导体封装可以包括具有第一表面和第二表面的基板，第二表面包括凹部，安装在第一表面上的第一半导体芯片，凹部外侧的第一球台面，凹部内的连接垫，第二表面 所述第二半导体芯片包括电连接到所述连接焊盘的通孔，以及电连接到所述通孔的第二焊盘。 半导体封装可以包括具有第一表面和第二表面的基板，第二表面包括凹部，安装在第一表面上的第一半导体芯片，凹部外侧的第一球台面，凹部内的连接垫，第二表面 半导体芯片，所述第二芯片包括电连接到所述连接焊盘的通孔，以及电连接到所述通孔的第二焊盘。
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公开(公告)号：US08338941B2
公开(公告)日：2012-12-25
申请号：US12805131
申请日：2010-07-14
申请人： Jinho Lee , Choongbin Yim , Jin-woo Park , Dae-young Choi , Mi-yeon Kim
发明人： Jinho Lee , Choongbin Yim , Jin-woo Park , Dae-young Choi , Mi-yeon Kim
IPC分类号： H01L23/48
CPC分类号： H01L21/76898 , H01L23/13 , H01L23/481 , H01L23/49822 , H01L23/49838 , H01L24/05 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/48 , H01L24/73 , H01L25/0657 , H01L25/18 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548 , H01L2224/0557 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/32014 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48095 , H01L2224/48227 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06527 , H01L2225/06541 , H01L2225/06572 , H01L2924/00014 , H01L2924/0002 , H01L2924/01033 , H01L2924/014 , H01L2924/078 , H01L2924/09701 , H01L2924/14 , H01L2924/1515 , H01L2924/15153 , H01L2924/15159 , H01L2924/15311 , H01L2924/1532 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second chip in the recessed portion, the second semiconductor chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via. A semiconductor package may include a substrate having first and second surfaces, the second surface including a recessed portion, a first semiconductor chip mounted on the first surface, a first ball land outside the recessed portion, a connection pad inside the recessed portion, a second semiconductor chip in the recessed portion, the second chip including a through via electrically connected to the connection pad, and a second ball land electrically connected to the through via.
摘要翻译： 半导体封装可以包括具有第一表面和第二表面的基板，第二表面包括凹部，安装在第一表面上的第一半导体芯片，凹部外侧的第一球台面，凹部内的连接垫，第二表面 所述第二半导体芯片包括电连接到所述连接焊盘的通孔，以及电连接到所述通孔的第二焊盘。 半导体封装可以包括具有第一表面和第二表面的基板，第二表面包括凹部，安装在第一表面上的第一半导体芯片，凹部外侧的第一球台面，凹部内的连接垫，第二表面 半导体芯片，所述第二芯片包括电连接到所述连接焊盘的通孔，以及电连接到所述通孔的第二焊盘。
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5.发明授权公开(公告)号：US09245867B2
公开(公告)日：2016-01-26
申请号：US14288440
申请日：2014-05-28
申请人： Choongbin Yim , Hae-Jung Yu , Taesung Park
发明人： Choongbin Yim , Hae-Jung Yu , Taesung Park
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/00 , H01L23/10 , H01L25/10 , H01L21/56 , H01L25/065
CPC分类号： H01L24/81 , H01L21/563 , H01L23/10 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2924/3511 , H01L2924/00012 , H01L2924/00
摘要： A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer.
摘要翻译： 包装封装（POP）电子设备可以包括第一和第二封装衬底，在第一和第二封装衬底之间提供电和机械耦合的焊料互连以及第一和第二封装衬底之间的第一和第二密封层。 第一和第二密封层可以是相应的第一和第二环氧树脂密封层。 此外，第二环氧树脂密封层可以包括助焊剂，并且第一环氧树脂密封层可以具有比第二环氧树脂密封层低的焊剂的浓度。
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6.发明授权公开(公告)号：US08779606B2
公开(公告)日：2014-07-15
申请号：US13734393
申请日：2013-01-04
申请人： Choongbin Yim , Hae-Jung Yu , Taesung Park
发明人： Choongbin Yim , Hae-Jung Yu , Taesung Park
CPC分类号： H01L24/81 , H01L21/563 , H01L23/10 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/12042 , H01L2924/15311 , H01L2924/15331 , H01L2924/18161 , H01L2924/3511 , H01L2924/00012 , H01L2924/00
摘要： A package-on-package (POP) electronic device may include first and second packaging substrates, a solder interconnection providing electrical and mechanical coupling between the first and second packaging substrates, and first and second sealing layers between the first and second packaging substrates. The first and second sealing layers may be respective first and second epoxy sealing layers. Moreover, the second epoxy sealing layer may include a solder flux agent, and the first epoxy sealing layer may have a lower concentration of the solder flux agent than the second epoxy sealing layer.
摘要翻译： 包装封装（POP）电子设备可以包括第一和第二封装衬底，在第一和第二封装衬底之间提供电和机械耦合的焊料互连以及第一和第二封装衬底之间的第一和第二密封层。 第一和第二密封层可以是相应的第一和第二环氧树脂密封层。 此外，第二环氧树脂密封层可以包括助焊剂，并且第一环氧树脂密封层可以具有比第二环氧树脂密封层低的焊剂的浓度。
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