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公开(公告)号：US20200273809A1
公开(公告)日：2020-08-27
申请号：US15781782
申请日：2017-04-10
Applicant: Credo Technology Group Limited
IPC: H01L23/552 , H03B5/12 , H01L23/00 , H01L23/538 , H01L23/498 , H01L23/64 , H01F17/00 , H04L7/00
Abstract: Disclosed microelectronic assemblies employ an integrated interposer cage to reduce electromagnetic interference with (and from) high-frequency components. One illustrative embodiment includes: at least one IC die having drive cores for a plurality of oscillators, the IC die attached in a flip-chip configuration to a (interposer) substrate, the substrate having: multiple inductors electrically coupled to said drive cores and each enclosed within a corresponding conductive cage integrated into the substrate to reduce mutual coupling between the inductors and noise coupled through substrate. An illustrative interposer embodiment includes: upper contacts arranged to electrically connect with micro bumps on at least one IC die; metallization and dielectric layers that form multiple inductors each surrounded by bars of a conductive cage; lower contacts arranged to electrically connect with bumps on a package substrate; and a substrate with a plurality of TSVs (through-silicon vias) that electrically couple to the lower contacts. Each of the bars includes: at least one of said TSVs, at least one via through the metallization and dielectric layers, and at least one upper contact.
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公开(公告)号：US11495898B2
公开(公告)日：2022-11-08
申请号：US17146350
申请日：2021-01-11
Applicant: Credo Technology Group Limited
Inventor： Xike Liu , Zhining Li , Xiangxiang Ye , Gaige Mei
Abstract: Connector paddle cards are provided with an improved wiring connection geometry that reduces impedance mismatch. One illustrative embodiment is a printed circuit board having, on at least one surface: edge connector traces arranged along a first edge for contacting electrical conductors in a socket connector; an outer set of electrodes arranged parallel to a second edge for attaching exposed ends of sheathed wires in a cable (“outer wires”); and an inner set of electrodes arranged parallel to the second edge for attaching exposed ends of sheathed wires in a cable (“inner wires”), with the electrodes in the inner set being staggered relative to the electrodes in the outer set.
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公开(公告)号：US10685942B2
公开(公告)日：2020-06-16
申请号：US16453128
申请日：2019-06-26
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Xike Liu , Mengying Ma
IPC: H04W72/04 , H01L25/10 , H01L23/00 , H01L23/498 , H01L23/66 , H01P9/00 , H04B1/40 , G06F30/3312 , G06F119/12 , G06F119/18
Abstract: A package trace design technique provides at least partial cancelation of reflections. In one illustrative method of providing a high-bandwidth chip-to-chip link with a first die coupled to a second die via a first substrate trace, an intermediate trace, and a second substrate trace, the method includes: (a) determining a first propagation delay for an electrical signal to traverse the first substrate trace, the electrical signal having a predetermined symbol interval; (b) determining a second propagation delay for the electrical signal to traverse the second substrate trace; and (c) setting a length for at least one of the first and second substrate traces, the length yielding a difference between the first and second propagation delays, the difference having a magnitude equal to half the predetermined symbol interval.
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Patent Agency Ranking
公开(公告)号：US10818608B2
公开(公告)日：2020-10-27
申请号：US15781782
申请日：2017-04-10
Applicant: Credo Technology Group Limited
IPC: H01L23/552 , H01L23/00 , H01L23/538 , H01L23/498 , H01L23/64 , H03B5/12 , H01F17/00 , H04L7/00
Abstract: Disclosed microelectronic assemblies employ an integrated interposer cage to reduce electromagnetic interference with (and from) high-frequency components. One illustrative embodiment includes: at least one IC die having drive cores for a plurality of oscillators, the IC die attached in a flip-chip configuration to a (interposer) substrate, the substrate having: multiple inductors electrically coupled to said drive cores and each enclosed within a corresponding conductive cage integrated into the substrate to reduce mutual coupling between the inductors and noise coupled through substrate. An illustrative interposer embodiment includes: upper contacts arranged to electrically connect with micro bumps on at least one IC die; metallization and dielectric layers that form multiple inductors each surrounded by bars of a conductive cage; lower contacts arranged to electrically connect with bumps on a package substrate; and a substrate with a plurality of TSVs (through-silicon vias) that electrically couple to the lower contacts. Each of the bars includes: at least one of said TSVs, at least one via through the metallization and dielectric layers, and at least one upper contact.
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公开(公告)号：US20200219828A1
公开(公告)日：2020-07-09
申请号：US16241481
申请日：2019-01-07
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Xike Liu
Abstract: Illustrative impedance matching circuits and methods provide enhanced performance without meaningfully increasing cost or areal requirements. One illustrative integrated circuit embodiment includes: a pin configured to connect to a substrate pad via a solder bump having a parasitic capacitance; an inductor that couples the pin to a transmit or receive circuit; a first electrostatic discharge (ESD) protection device electrically connected to a pin end of the inductor; and a second ESD protection device electrically connected to a circuit end of the inductor, where the first ESD protection device has a first capacitance that sums with the parasitic capacitance to equal a total capacitance coupled to the circuit end of the inductor.
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6.发明授权公开(公告)号：US09667407B1
公开(公告)日：2017-05-30
申请号：US15154567
申请日：2016-05-13
Applicant: Credo Technology Group Limited
Inventor： Xike Liu , Kei Peng , Chan Ho Yeung , YiFei Dai , Lawrence (Chi Fung) Cheng , Runsheng He
CPC classification number: H04L7/0079 , H01F17/0006 , H03B5/1212 , H03B5/1228 , H03L7/07 , H03L7/0807 , H03L7/0812 , H03L7/091 , H03L7/099 , H04B10/6164 , H04B10/6165 , H04L7/0025 , H04L7/007 , H04L7/02
Abstract: A multichannel receiver includes multiple receiver modules, each having: a voltage-controlled oscillator that generates a clock signal with a controllable frequency; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal in accordance with the sampling signal; a timing error estimator that operates on the digital receive signal to provide timing error estimates; a phase control filter that derives, from the timing error estimates, a phase control signal supplied to the phase interpolator, wherein the phase control signal minimizes a phase error between the sampling signal and the analog receive signal; and a frequency control filter that derives, from the timing error estimates, a frequency control signal for controlling the clock signal frequency, wherein the frequency control signal minimizes a frequency offset between the clock signal and the analog receive signal.
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公开(公告)号：US11756905B2
公开(公告)日：2023-09-12
申请号：US17194390
申请日：2021-03-08
Applicant: Credo Technology Group Limited
Inventor： Mengying Ma , Xike Liu , Xiangxiang Ye , Xin Wang
IPC: H01L23/66 , H03H11/28 , H03M9/00 , H01L23/00 , H01L23/498
CPC classification number: H01L23/66 , H01L23/49838 , H01L24/81 , H03H11/28 , H03M9/00 , H01L2223/6616 , H01L2224/81908 , H01L2224/81986 , H01L2924/30105 , H01L2924/30111
Abstract: An illustrative embodiment of a packaged integrated circuit includes: an integrated circuit chip having a SerDes signal pad; and a package substrate having a core via and an arrangement of micro-vias connecting the SerDes signal pad to an external contact for solder ball connection to a PCB trace. The core via has a first parasitic capacitance, the solder ball connection is associated with a second parasitic capacitance, and the arrangement of micro-vias provides a pi-network inductance that improves connection impedance matching. An illustrative method embodiment includes: obtaining an expected impedance of the PCB trace; determining parasitic capacitances of a core via and a solder ball connection to the PCB trace; minimizing the core via capacitance; calculating a pi-network inductance that improves impedance matching with the PCB trace; and adjusting a micro-via arrangement between the core via and the solder ball connection to provide the pi-network inductance.
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公开(公告)号：US10971458B2
公开(公告)日：2021-04-06
申请号：US16241481
申请日：2019-01-07
Applicant: CREDO TECHNOLOGY GROUP LIMITED
Inventor： Xike Liu
Abstract: Illustrative impedance matching circuits and methods provide enhanced performance without meaningfully increasing cost or areal requirements. One illustrative integrated circuit embodiment includes: a pin configured to connect to a substrate pad via a solder bump having a parasitic capacitance; an inductor that couples the pin to a transmit or receive circuit; a first electrostatic discharge (ESD) protection device electrically connected to a pin end of the inductor; and a second ESD protection device electrically connected to a circuit end of the inductor, where the first ESD protection device has a first capacitance that sums with the parasitic capacitance to equal a total capacitance coupled to the circuit end of the inductor.
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