摘要:
One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.
摘要:
One or more embodiments are related to a semiconductor device, comprising: a high-K dielectric material; and a nitrogen-doped silicon material disposed over said high-k dielectric material.
摘要:
Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
摘要:
The invention relates to a method for producing a PCM memory element and to a corresponding PCM element. The method of production comprises the following steps: providing a first and a second line device (Ma, Mb) underneath an insulating layer (10); providing a hole (5a, 5b) in the insulation layer (10), which partially exposes the first and the second line device (Ma, Mb); providing, as the respective lower electrode, a respective strip-shaped resistor element (20; 20′; 20″) on the wall of the hole (5a, 5b), which electrically contacts the exposed first or second line device (Ma, Mb): providing a filling (30) from an insulating material in the hole (5a, 5b) between the strip-shaped resistor elements (20; 20′; 20″); providing a layer (35) produced from a PCM material in the hole (5a, 5b), which electrically contacts the strip-shaped resistor elements (20; 20′; 20″) on their upper faces; providing a conducting layer (40) above the hole (5a, 5b) and the surrounding surface of the insulating layer (10): forming a sublithographic masking strip (50) on the conducting layer (40) above the hole (5a, 5b) and the surrounding surface of the insulating layer (210) at an angle to the direction of the first and second line device (Ma, Mb): forming segments of the mask strip (50); structuring the conducting layer (40) and the layer (35) produced from the PCM material while using the segments for forming the respective upper electrode from the conducting layer (40) and a PCM area of the layer (35) produced from PCM material lying between the upper and the lower electrode: removing the mask strip (50); and electrically connecting the upper electrode to an additional line device (80).
摘要:
Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
摘要:
Deep trench isolation structures and methods of formation thereof are disclosed. Several methods of and structures for increasing the threshold voltage of a parasitic transistor formed proximate deep trench isolation structures are described, including implanting a channel stop region into the bottom surface of the deep trench isolation structures, partially filling a bottom portion of the deep trench isolation structures with an insulating material, and/or filling at least a portion of the deep trench isolation structures with a doped polysilicon material.
摘要:
A memory cell includes a FinFET select device and a memory element. In some embodiments a memory cell has a contact element coupled between a surface of the fin and the memory element.
摘要:
One or more embodiments relate to a memory device, comprising: a substrate; a charge storage layer disposed over the substrate; and a control gate disposed over the charge storage layer, wherein the charge storage layer or the control gate layer comprises a carbon allotrope.
摘要:
A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.
摘要:
A method for fabricating a field-effect transistor is provided. The method includes forming a substrate region, forming two terminal regions at the substrate region, one terminal region being a source region and the other terminal region being a drain region, forming two electrically insulating insulating layers, which are arranged at mutually opposite sides of the substrate region and are adjoined by control regions, forming an electrically conductive connecting region, which electrically conductively connects one of the terminal regions and the substrate region the conductive connecting region comprising a metal-semiconductor compound, leveling a surface by chemical mechanical polishing after forming the control regions, etching-back the control regions after polishing, and performing a self-aligning method for forming the metal-semiconductor compound in the etched-back regions, on the substrate region, and on a terminal region.