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    Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device
    1.
    发明申请
    Memory Cell Arrangement, Method for Controlling a Memory Cell, Memory Array and Electronic Device 有权
    存储单元布置，用于控制存储单元，存储器阵列和电子设备的方法

    公开(公告)号：US20090059678A1

    公开(公告)日：2009-03-05

    申请号：US12049132

    申请日：2008-03-14

    申请人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

    发明人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

    IPC分类号： G11C16/02 ,  G11C11/40

    CPC分类号： G11C16/0425 ,  G11C16/10 ,  H01L29/66825 ,  H01L29/7881

    摘要： In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

    摘要翻译： 在本发明的一个实施例中，存储单元布置包括衬底和包括电荷存储存储单元结构和选择结构的至少一个存储单元。 存储单元布置还包括第一掺杂阱，第二掺杂阱和布置在衬底内的第三掺杂阱，其中电荷存储存储单元结构布置在第一掺杂阱中或上方，第一掺杂阱布置在 第二掺杂阱，并且第二掺杂阱被布置在第三掺杂阱内。 存储单元布置还包括与存储单元耦合并被配置为控制存储单元的控制电路，使得通过至少第一掺杂阱对电荷存储存储单元结构进行充电或放电来对电荷存储存储单元结构进行编程或擦除 。

    Semiconductor product and method for forming a semiconductor product
    4.
    发明申请
    Semiconductor product and method for forming a semiconductor product 审中-公开
    用于形成半导体产品的半导体产品和方法

    公开(公告)号：US20060286757A1

    公开(公告)日：2006-12-21

    申请号：US11153261

    申请日：2005-06-15

    申请人： John Power ,  Wolfram Langheinrich

    发明人： John Power ,  Wolfram Langheinrich

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/66636 ,  H01L27/11568 ,  H01L29/7834

    摘要： The invention provides a semiconductor product (25) and a method for forming the semiconductor product (25), the semiconductor product (25) comprising a transistor (1) having first (11) and second source/drain regions (12) being arranged at bottom surfaces (B) of recesses (R) in a substrate (2). Due to the depth (d) of the recesses (R) a vertical offset (29) between the source/drain regions (11, 12) and a gate dielectric (4) is achieved. The vertical offset (29) allows reducing a lateral offset (28) between the source/drain regions (11, 12) and the gate dielectric (4). Thereby, the substrate surface area required for a transistor is reduced. In particular in high voltage areas of semiconductor products like memory devices, substrate area is used more efficiently.

    摘要翻译： 本发明提供半导体产品（25）和形成半导体产品（25）的方法，所述半导体产品（25）包括具有第一（11）和第二源/漏区（12）的晶体管（1） 衬底（2）中凹部（R）的底表面（B）。 由于凹陷（R）的深度（d），实现了源极/漏极区域（11,12）和栅极电介质（4）之间的垂直偏移（29）。 垂直偏移（29）允许减小源极/漏极区域（11,12）和栅极电介质（4）之间的横向偏移（28）。 因此，晶体管所需的衬底表面积减小。 特别是在诸如存储器件的半导体产品的高电压区域中，更有效地使用衬底区域。

    Layer arrangement and memory arrangement
    5.
    发明申请
    Layer arrangement and memory arrangement 有权
    层布置和存储器布置

    公开(公告)号：US20060008959A1

    公开(公告)日：2006-01-12

    申请号：US10514168

    申请日：2003-05-15

    申请人： Peter Hagemeyer ,  Wolfram Langheinrich

    发明人： Peter Hagemeyer ,  Wolfram Langheinrich

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

    摘要： The disclosed embodiments relate to a method for the production of a layer arrangement, a layer arrangement and a memory arrangement. According to one aspect at least one respectively laterally defined first layer sequence is embodied on a first surface area of a substrate and at least one respectively laterally defined second layer sequence is embodied on a second surface area of the substrate in order to produce a layer arrangement. A first side wall having a first thickness is respectively produced from a first electrically insulating material on at least one partial area of the side walls of the first and second layer sequences. A second side wall layer having a second thickness is respectively produced from a second electrically insulating material on at least one partial area of the first side wall layers and the second side wall layers are removed from the first layer sequences.

    摘要翻译： 所公开的实施例涉及用于生产层布置，层布置和存储器布置的方法。 根据一个方面，至少一个分别横向限定的第一层序列被体现在衬底的第一表面区域上，并且至少一个分别横向限定的第二层序列被实施在衬底的第二表面区域上，以便产生层布置 。 具有第一厚度的第一侧壁分别由第一和第二层序列的侧壁的至少一个部分区域上的第一电绝缘材料制成。 在第一侧壁层的至少一个部分区域上分别由第二电绝缘材料制造具有第二厚度的第二侧壁层，并且从第一层序列中去除第二侧壁层。

    Method for fabricating embedded nonvolatile semiconductor memory cells
    6.
    发明授权
    Method for fabricating embedded nonvolatile semiconductor memory cells 有权
    嵌入式非易失性半导体存储单元的制造方法

    公开(公告)号：US06841448B2

    公开(公告)日：2005-01-11

    申请号：US10045278

    申请日：2002-01-14

    申请人： Oliver Gehring ,  Wolfram Langheinrich

    发明人： Oliver Gehring ,  Wolfram Langheinrich

    IPC分类号： H01L21/28 ,  H01L21/8246 ,  H01L27/105 ,  H01L21/8239 ,  H01L21/321

    CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11573 ,  Y10S438/981

    摘要： A method for fabricating embedded nonvolatile semiconductor memory cells is described. The method includes forming a first insulating layer on a substrate having a high-voltage region, a memory region and a logic region. The first insulating layer is removed in the memory region, and a second insulating layer is formed. A charge-storing layer is formed and patterned along with a third insulating layer. The first to third insulating layers and also the charge-storing layer are removed in the logic region. A fourth insulating layer is formed and a conductive control layer is formed and patterned.

    摘要翻译： 描述了一种用于制造嵌入式非易失性半导体存储单元的方法。 该方法包括在具有高电压区域，存储区域和逻辑区域的衬底上形成第一绝缘层。 在存储区域中去除第一绝缘层，形成第二绝缘层。 电荷存储层与第三绝缘层一起形成并图案化。 在逻辑区域中去除第一至第三绝缘层和电荷存储层。 形成第四绝缘层，形成导电控制层并构图。

    Method for fabricating a layer arrangement, layer arrangement and memory arrangement
    7.
    发明授权
    Method for fabricating a layer arrangement, layer arrangement and memory arrangement 有权
    用于制造层布置，层布置和存储器布置的方法

    公开(公告)号：US07713810B2

    公开(公告)日：2010-05-11

    申请号：US10514168

    申请日：2003-05-15

    申请人： Peter Hagemeyer ,  Wolfram Langheinrich

    发明人： Peter Hagemeyer ,  Wolfram Langheinrich

    IPC分类号： H01L21/8238

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11539

    摘要： The disclosed embodiments relate to a method for the production of a layer arrangement, a layer arrangement and a memory arrangement. According to one aspect at least one respectively laterally defined first layer sequence is embodied on a first surface area of a substrate and at least one respectively laterally defined second layer sequence is embodied on a second surface area of the substrate in order to produce a layer arrangement. A first side wall having a first thickness is respectively produced from a first electrically insulating material on at least one partial area of the side walls of the first and second layer sequences. A second side wall layer having a second thickness is respectively produced from a second electrically insulating material on at least one partial area of the first side wall layers and the second side wall layers are removed from the first layer sequences.

    摘要翻译： 所公开的实施例涉及用于生产层布置，层布置和存储器布置的方法。 根据一个方面，至少一个分别横向限定的第一层序列被体现在衬底的第一表面区域上，并且至少一个分别横向限定的第二层序列被实施在衬底的第二表面区域上，以便产生层布置 。 具有第一厚度的第一侧壁分别由第一和第二层序列的侧壁的至少一个部分区域上的第一电绝缘材料制成。 在第一侧壁层的至少一个部分区域上分别由第二电绝缘材料制造具有第二厚度的第二侧壁层，并且从第一层序列中去除第二侧壁层。

    Flash memory cell with buried floating gate and method for operating such a flash memory cell
    8.
    发明授权
    Flash memory cell with buried floating gate and method for operating such a flash memory cell 失效
    具有埋置浮动栅极的闪存单元和用于操作这样的闪存单元的方法

    公开(公告)号：US07064377B2

    公开(公告)日：2006-06-20

    申请号：US10808219

    申请日：2004-03-24

    申请人： Peter Hagemeyer ,  Wolfram Langheinrich

    发明人： Peter Hagemeyer ,  Wolfram Langheinrich

    IPC分类号： H01L29/788

    CPC分类号： H01L29/42336

    摘要： A programmable read-only memory cell and method of operating the programmable read-only memory cell. In one embodiment, the programmable read-only memory cell comprises a floating gate arranged in a trench, an epitaxial channel layer formed on the floating gate, the channel layer connecting a source electrode to a drain electrode, and a selection gate arranged above the channel line.

    摘要翻译： 一种可编程只读存储单元和操作可编程只读存储单元的方法。 在一个实施例中，可编程只读存储器单元包括布置在沟槽中的浮置栅极，形成在浮置栅极上的外延沟道层，将源极连接到漏极电极的沟道层以及布置在沟道上方的选择栅极 线。

    Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
    10.
    发明授权
    Memory cell arrangement, method for controlling a memory cell, memory array and electronic device 有权
    存储单元布置，用于控制存储单元的方法，存储器阵列和电子设备

    公开(公告)号：US08320191B2

    公开(公告)日：2012-11-27

    申请号：US12049132

    申请日：2008-03-14

    申请人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

    发明人： Robert Strenz ,  Wolfram Langheinrich ,  Mayk Roehrich ,  Robert Wiesner

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0425 ,  G11C16/10 ,  H01L29/66825 ,  H01L29/7881

    摘要： In an embodiment of the invention, a memory cell arrangement includes a substrate and at least one memory cell including a charge storing memory cell structure and a select structure. The memory cell arrangement further includes a first doping well, a second doping well and a third doping well arranged within the substrate, wherein the charge storing memory cell structure is arranged in or above the first doping well, the first doping well is arranged within the second doping well, and the second doping well is arranged within the third doping well. The memory cell arrangement further includes a control circuit coupled with the memory cell and configured to control the memory cell such that the charge storing memory cell structure is programmed or erased by charging or discharging the charge storing memory cell structure via at least the first doping well.

    摘要翻译： 在本发明的一个实施例中，存储单元布置包括衬底和包括电荷存储存储单元结构和选择结构的至少一个存储单元。 存储单元布置还包括第一掺杂阱，第二掺杂阱和布置在衬底内的第三掺杂阱，其中电荷存储存储单元结构布置在第一掺杂阱中或上方，第一掺杂阱布置在 第二掺杂阱，并且第二掺杂阱被布置在第三掺杂阱内。 存储单元布置还包括与存储单元耦合并被配置为控制存储单元的控制电路，使得通过至少第一掺杂阱对电荷存储存储单元结构进行充电或放电来对电荷存储存储单元结构进行编程或擦除 。