公开(公告)号：US5572470A

公开(公告)日：1996-11-05

申请号：US438349

申请日：1995-05-10

申请人： David C. McClure ,  Thomas Teel

发明人： David C. McClure ,  Thomas Teel

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C29/808 ,  G11C29/84 ,  G11C29/846

摘要： An apparatus maps one of a plurality of redundant memory columns, each having a redundant memory cell, to an address of a defective memory column in a memory device that communicates with an external data bus having one or more data-bit lines and an address bus. An address decoder receives an address signal on the address bus and generates an enable signal to enable the redundant cell of the redundant column when the value of the address signal equals the address of the defective memory column. A bit-select bus has one or more bit-select lines each associated with one of the data-bit lines. Each bit-select line can carry a bit-select signal. Each of a plurality of bit-line selectors is associated with one of the redundant columns and communicates with the bit-select bus. In response to an associated enable signal, each bit-line selector can generate the bit-select signal on the bit-select line associated with a desired data-bit line. An interface circuit couples the redundant cell to the desired data-bit line in response to the bit-select signal.

摘要翻译： 一种装置将具有冗余存储单元的多个冗余存储器列之一映射到与具有一个或多个数据位线和地址总线的外部数据总线进行通信的存储器件中的缺陷存储器列的地址 。 地址解码器在地址总线上接收地址信号，并且当地址信号的值等于有缺陷的存储器列的地址时，产生使能信号以使能冗余列的冗余单元。 位选择总线具有每个与数据位线之一相关联的一个或多个位选择线。 每个位选择行可以携带位选择信号。 多个位线选择器中的每一个与冗余列中的一个相关联，并与位选择总线通信。 响应于相关联的使能信号，每个位线选择器可以在与期望的数据位线相关联的位选择线上产生位选择信号。 接口电路响应于位选择信号将冗余单元耦合到期望的数据位线。

公开(公告)号：US5574688A

公开(公告)日：1996-11-12

申请号：US438903

申请日：1995-05-10

申请人： David C. McClure ,  Thomas Teel

发明人： David C. McClure ,  Thomas Teel

IPC分类号： G11C29/00 ,  G11C13/00

CPC分类号： G11C29/80 ,  G11C29/84

摘要： A memory device, which communicates with external address and data buses, includes a circuit for mapping a redundant memory column having a redundant memory cell to an address of a defective memory column. An enable line communicates with the redundant memory column and selectively carries active and inactive signal levels for respectively enabling and disabling communication between the data bus and the redundant memory cell. An address decoder receives an address signal on the address bus and generates the active level on the enable line when the value of the address signal equals the address of the defective memory cell. A driver precharges the enable line to the inactive level while the address signal is invalid.

摘要翻译： 与外部地址和数据总线通信的存储器件包括用于将具有冗余存储器单元的冗余存储器列映射到有缺陷的存储器列的地址的电路。 使能线与冗余存储器列通信，并选择性地承载有源和非活动信号电平，以分别启用和禁用数据总线与冗余存储单元之间的通信。 地址解码器在地址总线上接收地址信号，并且当地址信号的值等于有缺陷的存储单元的地址时，在使能线上产生有效电平。 当地址信号无效时，驱动器将使能线路预充电到无效电平。

公开(公告)号：US07224600B2

公开(公告)日：2007-05-29

申请号：US10783935

申请日：2004-02-20

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C7/24

摘要： A circuit includes a volatile memory array and a logic circuit operable to detect a memory array tamper situation and generate at least one control signal responsive thereto. Circuitry associated with each of the individual cells within the volatile memory array responds to the at least one control signal by destroying any data stored by the associated memory cell. Data is destroyed using one of several options including: shorting a true node of the latch to a complement node of the latch, shorting the true and complement nodes of the latch to a bit line and a complement bit line, shorting one of the true/complement nodes of the latch to a reference voltage, shorting both the true and complement nodes of the latch to at least one reference voltage, coupling a first and second positive reference voltage inputs to a positive/ground voltage supply, or shorting the bit line to a reference voltage while the pass gate is activated.

摘要翻译： 电路包括易失性存储器阵列和可操作以检测存储器阵列篡改状况并且响应于此产生至少一个控制信号的逻辑电路。 与易失性存储器阵列中的每个单元相关联的电路通过破坏由相关联的存储器单元存储的任何数据来响应于至少一个控制信号。 数据被破坏使用以下几个选项之一，包括：将锁存器的真实节点短接到锁存器的补码节点，将锁存器的真实和补码节点短路到位线和补码位线，将真/ 将锁存器的节点补充为参考电压，将锁存器的真实和补码节点都短路到至少一个参考电压，将第一和第二正参考电压输入耦合到正/接地电压源，或将位线短路到 通过门被激活时的参考电压。

公开(公告)号：US07132767B2

公开(公告)日：2006-11-07

申请号：US10754023

申请日：2004-01-08

申请人： David C. McClure ,  Tom Youssef

发明人： David C. McClure ,  Tom Youssef

IPC分类号： H01H47/00

CPC分类号： G11C5/141 ,  Y10T307/615 ,  Y10T307/625 ,  Y10T307/826

摘要： An integrated circuit and method for providing a switchover from the primary power source to the secondary power source to prevent a volatile element from losing stored data. The integrated circuit includes a forced power source switchover circuit for detecting that the supply level of the primary power source drops below a predefined threshold level. A switchover circuit on the integrated circuit initiates a switchover operation based upon the forced power source switchover circuit detecting that the supply level being received from the primary power source drops below the predefined threshold level. The detection by the forced power source switchover circuitry may occur on a signal level that transitions faster than a predetermined negative rate of change. The integrated circuit may be incorporated in any system having volatile elements, such as memory or a clock.

摘要翻译： 一种用于提供从主电源到次电源的切换以防止易失性元件丢失存储的数据的集成电路和方法。 集成电路包括强制电源切换电路，用于检测主电源的电源电平低于预定阈值电平。 集成电路中的切换电路基于强制电源切换电路检测到从主电源接收的电源电平下降到低于预定阈值水平的情况下开始切换操作。 强制电源切换电路的检测可能发生在比预定的负变化率更快地转变的信号电平上。 集成电路可以并入具有诸如存储器或时钟之类的易失性元件的任何系统中。

公开(公告)号：US06603338B1

公开(公告)日：2003-08-05

申请号：US09183593

申请日：1998-10-30

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： H03K3017

CPC分类号： H03K5/1252 ,  G11C8/06 ,  G11C11/418 ,  H03K5/1534

摘要： A substantially noise-free address input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates both a logical true and complement representation of an address input signal and includes timing circuitry to place the logical true and complement signals in the same deasserting logical state for a predetermined period of time prior to asserting either the logical true signal or the logical complement signal, in response to a signal edge transition appearing on the address input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the logical true and complement signals.

摘要翻译： 用于异步设备（例如静态随机存取存储器（SRAM））的基本上无噪声的地址输入缓冲器。 输入缓冲器产生地址输入信号的逻辑真和补码表示，并且包括定时电路，用于将逻辑真和补码信号置于相同的解除逻辑状态中一段预定的时间段，然后再将逻辑真信号或 逻辑补码信号，响应于地址输入信号上出现的信号边沿转换。 输入缓冲器还包括用于响应于逻辑真和补码信号的产生而产生初始化信号的边沿转换检测（ETD）电路。

公开(公告)号：US06294939B1

公开(公告)日：2001-09-25

申请号：US09183595

申请日：1998-10-30

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： H03K3017

CPC分类号： G11C7/1087 ,  G11C7/1078 ,  G11C11/419 ,  H03K5/1534

摘要： A substantially noise-free data input buffer for an asynchronous device, such as a static random access memory (SRAM). The input buffer generates either a logical true or complement output signal representation of a data input signal and includes timing circuitry to delay an edge transition on the output signal for a predetermined period of time in response to a signal edge transition appearing on the data input signal. The input buffer further includes edge transition detection (ETD) circuitry for generating an initialization signal in response to the generation of the data output signal.

摘要翻译： 用于异步设备（例如静态随机存取存储器（SRAM））的基本上无噪声的数据输入缓冲器。 输入缓冲器产生数据输入信号的逻辑真或补输出信号表示，并且包括定时电路，以响应于在数据输入信号上出现的信号边沿转变，在输出信号上延迟预定时间段的边沿转换 。 输入缓冲器还包括用于响应于数据输出信号的产生产生初始化信号的边沿转移检测（ETD）电路。

公开(公告)号：US06281734B1

公开(公告)日：2001-08-28

申请号：US09476036

申请日：1999-12-31

申请人： David C. McClure ,  Rong Yin

发明人： David C. McClure ,  Rong Yin

IPC分类号： H03L500

CPC分类号： G05F3/242

摘要： A reference voltage trim circuit includes a voltage follower receiving the reference voltage to be trimmed, with one or more resistive loads providing predefined voltage shifts serially connected between the output of the voltage follower and the output of the trim circuit. The voltage follower includes a current mirror differential amplifier receiving the reference voltage at one input and the output of the voltage follower at the other input, and a transistor with a resistive load connected between the power supply voltages and receiving the output of the current mirror differential amplifier at the transistor's gate. The resistive loads provide varying preselected voltage drop and are each shunted by corresponding fuses, with the entire series of resistive loads shunted by a master fuse. To trim the reference voltage, at least the master fuse is blown, together with the fuse(s) shunting resistive loads which combine to result in the desired trim voltage. Pass gates control which end of the resistive load series is connected to the output of the voltage follower and which is connected to the output of the trim circuit. To decrement the reference voltage, a first end is connected to the output of the voltage follower and the second end is connected to trim circuit output; to increment the reference voltage, the second end of the resistive load series is connected to the voltage follower output and the first end is connected to the trim circuit output.

摘要翻译： 参考电压调整电路包括接收要修整的参考电压的电压跟随器，其中一个或多个电阻负载提供串联连接在电压跟随器的输出端和微调电路的输出之间的预定电压偏移。 电压跟随器包括电流反射镜差分放大器，其在一个输入处接收参考电压，并在另一个输入端接收电压跟随器的输出;以及晶体管，其电阻负载连接在电源电压之间并接收电流镜差分的输出 放大器在晶体管的门。 电阻负载提供变化的预选电压降，并且每个分压由对应的保险丝分流，整个电阻负载系列由主保险丝分流。 为了修整参考电压，至少主保险丝与熔断器一起分流电阻性负载，结合起来产生所需的调整电压。 通路控制电阻负载系列的哪一端连接到电压跟随器的输出端并连接到微调电路的输出。 为了减小参考电压，第一端连接到电压跟随器的输出端，第二端连接到微调电路输出; 为了增加参考电压，电阻负载系列的第二端连接到电压跟随器输出，第一端连接到微调电路输出。

公开(公告)号：US6034917A

公开(公告)日：2000-03-07

申请号：US183589

申请日：1998-10-30

申请人： David C. McClure ,  Tom Youssef

发明人： David C. McClure ,  Tom Youssef

IPC分类号： G11C7/22 ,  G11C11/419 ,  G11C8/00

CPC分类号： G11C11/419 ,  G11C7/22

摘要： A control circuit for terminating a memory access cycle in a memory block having at least one memory cell is disclosed. The at least one memory cell has unique process characteristics. The control circuit includes a memory block activation circuit for generating a memory block activation signal. The memory block activation circuit includes a reset circuit for terminating the memory block activation signal when activated. The control circuit also includes a memory access cycle tracking circuit, responsive to the memory block activation signal, for generating a reset signal. The memory access cycle tracking circuit includes the unique process characteristics of the at least one memory cell for tracking an operation of the at least one memory cell. The reset signal activates the reset circuit so as to terminate the memory block activation signal and terminate the memory access cycle in the memory block.

摘要翻译： 公开了一种用于在具有至少一个存储器单元的存储器块中终止存储器访问周期的控制电路。 至少一个存储单元具有独特的工艺特性。 控制电路包括用于产生存储块激活信号的存储块激活电路。 存储器块激活电路包括用于当激活时终止存储块激活信号的复位电路。 控制电路还包括响应于存储块激活信号的存储器访问周期跟踪电路，用于产生复位信号。 存储器访问周期跟踪电路包括用于跟踪至少一个存储器单元的操作的至少一个存储器单元的唯一的处理特性。 复位信号激活复位电路，以终止存储器块激活信号并终止存储器块中的存储器访问周期。

公开(公告)号：US5898235A

公开(公告)日：1999-04-27

申请号：US775611

申请日：1996-12-31

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G11C11/413 ,  G05F1/56 ,  G05F3/24 ,  G05F3/26 ,  G11C5/14 ,  G11C11/407 ,  H03K5/153

CPC分类号： G11C5/147 ,  G05F3/262 ,  Y10T307/615

摘要： An integrated circuit device such as an SRAM operating in a battery backup mode, or operating in a quiescent mode when deselected in the operation of a portable electronic device, includes a power dissipation control circuit that reduces the voltage on an internal power supply node so that the memory array is powered at a minimum level sufficient to retain the data stored therein intact.

摘要翻译： 在便携式电子设备的操作中取消选择时，以电池备份模式操作的SRAM或以静止模式操作的集成电路器件包括功率耗散控制电路，其降低内部电源节点上的电压，使得 存储器阵列以足以保持其中存储的数据完整的最小水平供电。

公开(公告)号：US5883008A

公开(公告)日：1999-03-16

申请号：US979019

申请日：1997-11-26

申请人： David C. McClure

发明人： David C. McClure

IPC分类号： G01R31/28 ,  G01R31/30 ,  G01R31/3185 ,  G06F11/22 ,  G11C29/00 ,  G11C29/26 ,  G11C29/56 ,  H01L23/58 ,  H01L21/00

CPC分类号： H01L22/32 ,  G01R31/30 ,  G01R31/318505 ,  G01R31/318511 ,  G11C29/26 ,  G06F11/2273 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A semiconductor integrated-circuit die includes a substrate of semiconductor material that has an edge. A conductive layer is disposed on the substrate, and a first insulator layer is disposed between the said substrate and the conductive layer. A functional circuit is disposed in the die. A conductive path is disposed beneath the insulator layer and is coupled to the circuit, the conductive path having an end portion that is located substantially at the edge of the substrate. The wafer on which the die is disposed has one or more signal lines that run along the scribe lines of the wafer. Before the die is scribed from the wafer, the conductive path couples the circuit on the die to one of these signal lines. The end portion of the conductive path is formed when the die is scribed from the wafer.

摘要翻译： 半导体集成电路管芯包括具有边缘的半导体材料的衬底。 导电层设置在基板上，第一绝缘层设置在所述基板和导电层之间。 功能电路设置在模具中。 导电路径设置在绝缘体层下方并且耦合到电路，导电路径具有基本位于衬底边缘处的端部。 其上设置管芯的晶片具有沿着晶片的划线延伸的一条或多条信号线。 在从晶片划线之前，导电路径将管芯上的电路耦合到这些信号线之一。 导电路径的端部在晶片被刻划时形成。