公开(公告)号：US20100110786A1

公开(公告)日：2010-05-06

申请号：US12585870

申请日：2009-09-28

申请人： Dongku Kang ,  Sungsoo Lee

发明人： Dongku Kang ,  Sungsoo Lee

IPC分类号： G11C16/06 ,  G11C7/04 ,  G11C5/14 ,  G11C7/06 ,  G11C29/00

CPC分类号： G11C7/04 ,  G11C16/0483 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： Provided are a nonvolatile memory device and a memory test system. The nonvolatile memory device includes a temperature compensator to calculate a trim value for regulating a characteristic of the nonvolatile memory device that varies with temperature in response to a test signal. The memory test system includes a plurality of nonvolatile memories and a tester. Each of the nonvolatile memories includes a temperature compensator. The tester tests the plurality of nonvolatile memories. The temperature compensator calculates a trim value for regulating a characteristic of the nonvolatile memory device that varies with temperature in response to a test signal of the tester.

摘要翻译： 提供了非易失性存储器件和存储器测试系统。 非易失性存储器件包括温度补偿器，用于根据测试信号计算用于调节随温度变化的非易失性存储器件的特性的微调值。 存储器测试系统包括多个非易失性存储器和测试器。 每个非易失性存储器包括温度补偿器。 测试仪测试多个非易失性存储器。 温度补偿器根据测试仪的测试信号计算用于调节随温度变化的非易失性存储器件的特性的微调值。

公开(公告)号：US08559229B2

公开(公告)日：2013-10-15

申请号：US13246040

申请日：2011-09-27

申请人： Seung-Gum Kim ,  Ohsuk Kwon ,  Dongku Kang ,  Tae-Young Kim ,  Jaewoo Im ,  Moosung Kim ,  Jae-Duk Yu

发明人： Seung-Gum Kim ,  Ohsuk Kwon ,  Dongku Kang ,  Tae-Young Kim ,  Jaewoo Im ,  Moosung Kim ,  Jae-Duk Yu

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/30 ,  G11C16/3436

摘要： A word line voltage generating method of a flash memory which includes generating a program voltage using a positive voltage generator; generating a plurality of negative program verification voltages corresponding to a plurality of negative data states using a negative voltage generator; and generating at least one or more program verification voltages corresponding to at least one or more states using the positive voltage generator. Generating a plurality of negative program verification voltages includes generating a first negative verification voltage; discharging an output of the negative voltage generator to become higher than the first negative verification voltage; and performing a negative charge pumping operation until an output of the negative voltage generator reaches a second negative verification voltage level.

摘要翻译： 一种闪存的字线电压产生方法，包括使用正电压发生器产生编程电压; 使用负电压发生器产生对应于多个负数据状态的多个负编程验证电压; 以及使用所述正电压发生器产生对应于至少一个或多个状态的至少一个或多个程序验证电压。 生成多个负编程验证电压包括产生第一负验证电压; 将负电压发生器的输出放电到高于第一负验证电压; 并执行负电荷泵送操作直到负电压发生器的输出达到第二负验证电压电平。

公开(公告)号：US20090231914A1

公开(公告)日：2009-09-17

申请号：US12232150

申请日：2008-09-11

申请人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

发明人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

IPC分类号： G11C16/06 ,  G11C16/00

CPC分类号： G11C16/26 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2211/5621

摘要： Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit.

摘要翻译： 公开了一种存储器件和存储器数据读取方法。 存储器件可以包括多位单元阵列，阈值电压检测单元，被配置为从多个阈值电压间隔中检测包括多位单元阵列的多位单元的阈值电压的第一阈值电压间隔， 单元，被配置为基于检测到的第一阈值电压间隔来确定第一位层的数据;以及错误检测单元，被配置为检测第一位层的数据的错误位。 在这种情况下，确定单元可以使用具有与检测到的错误位不同的第一位层的值的第二阈值电压间隔来确定第二位层的数据，并且最接近对应于多个位单元的阈值电压 检测到错误位。

公开(公告)号：US10007603B2

公开(公告)日：2018-06-26

申请号：US14697115

申请日：2015-04-27

申请人： Han-Jun Lee ,  Dongku Kang

发明人： Han-Jun Lee ,  Dongku Kang

IPC分类号： G06F12/02 ,  G11C16/10 ,  G11C7/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/28

CPC分类号： G06F12/0246 ,  G06F2212/7208 ,  G11C7/1039 ,  G11C16/10 ,  G11C16/26 ,  G11C16/28 ,  G11C16/32

摘要： A nonvolatile memory device includes a mat including a plurality of memory blocks, an address decoder configured to select one of the memory blocks in response to an address, an input/output circuit including first and second page buffers configured to program a plurality of data pages into a single physical page of the selected one of the memory blocks or store the plurality of data pages read from the single physical page of the selected one of the memory blocks, and a control logic configured to perform a dumping operation at an other one of the first page buffers and second page buffers when a data input operation or a data output operation is performed at one of the first and second page buffers of the input/output circuit. The input/output circuit includes a plurality of page buffers. The plurality of page buffers include the first and second page buffers.

公开(公告)号：US08339847B2

公开(公告)日：2012-12-25

申请号：US12861855

申请日：2010-08-24

申请人： Youngho Lim ,  Dongku Kang ,  HyeongJun Kim

发明人： Youngho Lim ,  Dongku Kang ,  HyeongJun Kim

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/3418 ,  G11C2211/5648

摘要： A method of programming a non-volatile memory including N-bit multi-level cell (MLC) memory cells includes executing first through (N−1)th page programming operations, using an incremental step pulse programming (ISPP) method, to program first through (N−1)th data pages in the MLC memory cells, where each of the first through (N−1)th page programming operations includes an erase programming of erase cells among the MLC memory cells. The method further includes executing an Nth page programming operation, using the ISPP method, to program an Nth data page in the MLC memory cells.

摘要翻译： 一种编程包括N位多电平单元（MLC）存储器单元的非易失性存储器的方法包括使用增量步进脉冲编程（ISPP）方法执行第一至第（N-1）页编程操作，以首先编程 通过MLC存储器单元中的第（N-1）个数据页，其中第一至第（N-1）页编程操作中的每一个包括MLC存储单元中的擦除单元的擦除编程。 该方法还包括使用ISPP方法执行第N页面编程操作来编程MLC存储器单元中的第N个数据页。

公开(公告)号：US07903459B2

公开(公告)日：2011-03-08

申请号：US12232150

申请日：2008-09-11

申请人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

发明人： Donghun Yu ,  Kyoung Lae Cho ,  Dongku Kang ,  Dong Hyuk Chae ,  Jun Jin Kong

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2211/5621

摘要： Disclosed are a memory device and a memory data reading method. The memory device may include a multi-bit cell array, a threshold voltage detecting unit configured to detect first threshold voltage intervals including threshold voltages of multi-bit cells of the multi-bit cell array from among a plurality of threshold voltage intervals, a determination unit configured to determine data of a first bit layer based on the detected first threshold voltage intervals, and an error detection unit configured to detect an error bit of the data of the first bit layer. In this instance, the determination unit may determine data of a second bit layer using a second threshold voltage interval having a value of the first bit layer different from the detected error bit and being nearest to a threshold voltage of a multi-bit cell corresponding to the detected error bit.

摘要翻译： 公开了一种存储器件和存储器数据读取方法。 存储器件可以包括多位单元阵列，阈值电压检测单元，被配置为从多个阈值电压间隔中检测包括多位单元阵列的多位单元的阈值电压的第一阈值电压间隔， 单元，被配置为基于检测到的第一阈值电压间隔来确定第一位层的数据;以及错误检测单元，被配置为检测第一位层的数据的错误位。 在这种情况下，确定单元可以使用具有与检测到的错误位不同的第一位层的值的第二阈值电压间隔来确定第二位层的数据，并且最接近对应于多个位单元的阈值电压 检测到错误位。

公开(公告)号：US20090027971A1

公开(公告)日：2009-01-29

申请号：US12073842

申请日：2008-03-11

申请人： Seung-Hwan Song ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Seung Hoon Lee ,  Dongku Kang

发明人： Seung-Hwan Song ,  Dong Hyuk Chae ,  Jun Jin Kong ,  Seung Hoon Lee ,  Dongku Kang

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C2211/5634

摘要： In reading data from a memory cell, a determining circuit determines whether a received voltage value is within at least one first voltage range through a one-time read operation using a semiconductor device that senses an output current corresponding to the received voltage value. The at least one first voltage range includes a first upper limit voltage value and a first lower limit voltage value. A data value of the memory cell is set as a first data value when the received voltage value is within the specific voltage range.

摘要翻译： 在从存储单元读取数据时，确定电路通过使用感测与接收电压值对应的输出电流的半导体器件的一次读取操作来确定接收电压值是否在至少一个第一电压范围内。 所述至少一个第一电压范围包括第一上限电压值和第一下限电压值。 当接收电压值在特定电压范围内时，存储单元的数据值被设置为第一数据值。

公开(公告)号：US08634246B2

公开(公告)日：2014-01-21

申请号：US12961207

申请日：2010-12-06

申请人： Dongku Kang ,  Tae-Young Kim

发明人： Dongku Kang ,  Tae-Young Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/16 ,  G11C16/344

摘要： A method of operating a non-volatile memory device includes performing an erasing operation to memory cells associated with a string selection line (SSL), the memory cells associated with the SSL constituting a memory block, and verifying the erasing operation to second memory cells associated with a second word line (WL) after verifying the erasing operation to first memory cells associated with a first word line (WL).

摘要翻译： 操作非易失性存储器件的方法包括对与字符串选择行（SSL）相关联的存储器单元执行擦除操作，与构成存储器块的SSL相关联的存储器单元，以及验证与相关联的第二存储器单元的擦除操作 在对与第一字线（WL）相关联的第一存储器单元进行擦除操作之后，使用第二字线（WL）。

公开(公告)号：US09406386B2

公开(公告)日：2016-08-02

申请号：US14797203

申请日：2015-07-13

申请人： Jae-Duk Yu ,  Chul Bum Kim ,  Dongku Kang

发明人： Jae-Duk Yu ,  Chul Bum Kim ,  Dongku Kang

IPC分类号： G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C8/12 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3418 ,  G11C2211/5648

摘要： A data storage device includes a nonvolatile memory having a plurality of first memory cells connected to a first word line and a plurality of second memory cells connected to a second word line. A memory controller divides first data to be programmed in the first memory cells into first and second data groups and divides second data to be programmed in the second memory cells into third and fourth data groups. The nonvolatile memory device performs a third program operation of the second data group and a fourth program operation of the fourth data group after sequentially performing a first program operation of the first data group and a second program operation of the third data group.

摘要翻译： 数据存储装置包括具有连接到第一字线的多个第一存储器单元和连接到第二字线的多个第二存储器单元的非易失性存储器。 存储器控制器将要在第一存储器单元中编程的第一数据划分成第一和第二数据组，并将要在第二存储器单元中编程的第二数据划分成第三和第四数据组。 在顺序执行第一数据组的第一编程操作和第三数据组的第二编程操作之后，非易失性存储器件执行第二数据组的第三程序操作和第四数据组的第四编程操作。

公开(公告)号：US08331145B2

公开(公告)日：2012-12-11

申请号：US12722718

申请日：2010-03-12

申请人： Dongku Kang

发明人： Dongku Kang

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5621

摘要： A method of programming a nonvolatile memory device comprises selectively programming memory cells from a first state to a second state based on lower bit data, selectively programming the memory cells from the second state to an intermediate state corresponding to the lower bit data, and selectively programming the memory cells from the intermediate state to a third or fourth state based on upper bit data.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括：基于较低位数据选择性地将存储器单元从第一状态编程到第二状态，有选择地将存储器单元从第二状态编程到对应于较低位数据的中间状态，以及选择性编程 存储单元基于高位数据从中间状态到第三或第四状态。