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公开(公告)号：US20110097870A1
公开(公告)日：2011-04-28
申请号：US12540457
申请日：2009-08-13
IPC分类号： H01L21/8234
CPC分类号： H01L27/0688 , H01L21/76804 , H01L21/76898 , H01L23/481 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
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公开(公告)号：US07723851B2
公开(公告)日：2010-05-25
申请号：US11853118
申请日：2007-09-11
IPC分类号： H01L23/48
CPC分类号： H01L21/76802 , H01L21/76804 , H01L27/0688 , H01L2224/80896 , H01L2224/9202
摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
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3.发明授权Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias 有权使用超深通孔制造超深通孔和三维集成电路的方法公开(公告)号：US07704869B2
公开(公告)日：2010-04-27
申请号：US11853139
申请日：2007-09-11
IPC分类号： H01L21/4763
CPC分类号： H01L27/0688 , H01L21/76804 , H01L21/76898 , H01L23/481 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
摘要翻译： 通过多个电介质层开口形成高纵横比的方法，高纵横比导电通孔，形成三维集成电路的方法和三维集成电路。 所述方法包括形成至少四个电介质层的叠层，并且用对第二和第四电介质层选择性的工艺蚀刻第一和第三电介质层，用对第一和第二电介质层选择的工艺蚀刻第二和第三电介质层。 有利地，用于蚀刻第三介电层的工艺对第一介电层基本不具有选择性。
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公开(公告)号：US20090065941A1
公开(公告)日：2009-03-12
申请号：US11853118
申请日：2007-09-11
IPC分类号： H01L23/48
CPC分类号： H01L21/76802 , H01L21/76804 , H01L27/0688 , H01L2224/80896 , H01L2224/9202
摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
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5.发明授权Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias 有权使用超深通孔制造超深通孔和三维集成电路的方法公开(公告)号：US09318375B2
公开(公告)日：2016-04-19
申请号：US12540490
申请日：2009-08-13
IPC分类号： H01L23/48 , H01L21/768 , H01L27/06
CPC分类号： H01L21/76802 , H01L21/76804 , H01L27/0688 , H01L2224/80896 , H01L2224/9202
摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
摘要翻译： 通过多个电介质层开口形成高纵横比的方法，高纵横比导电通孔，形成三维集成电路的方法和三维集成电路。 所述方法包括形成至少四个电介质层的叠层，并且用对第二和第四电介质层选择性的工艺蚀刻第一和第三介电层，用对第一和第二电介质层选择的工艺蚀刻第二和第三介电层。 有利地，用于蚀刻第三介电层的工艺对第一介电层基本不具有选择性。
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6.发明申请METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS 有权使用超深度VIAS制造超深度VIAS和三维集成电路的方法公开(公告)号：US20110147939A1
公开(公告)日：2011-06-23
申请号：US12540490
申请日：2009-08-13
IPC分类号： H01L23/522
CPC分类号： H01L21/76802 , H01L21/76804 , H01L27/0688 , H01L2224/80896 , H01L2224/9202
摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
摘要翻译： 通过多个电介质层开口形成高纵横比的方法，高纵横比导电通孔，形成三维集成电路的方法和三维集成电路。 所述方法包括形成至少四个电介质层的叠层，并且用对第二和第四电介质层选择性的工艺蚀刻第一和第三介电层，用对第一和第二电介质层选择的工艺蚀刻第二和第三电介质层。 有利地，用于蚀刻第三介电层的工艺对第一介电层基本不具有选择性。
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7.发明授权Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias 有权使用超深通孔制造超深通孔和三维集成电路的方法公开(公告)号：US07955967B2
公开(公告)日：2011-06-07
申请号：US12540457
申请日：2009-08-13
IPC分类号： H01L21/4763
CPC分类号： H01L27/0688 , H01L21/76804 , H01L21/76898 , H01L23/481 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
摘要翻译： 通过多个电介质层开口形成高纵横比的方法，高纵横比导电通孔，形成三维集成电路的方法和三维集成电路。 所述方法包括形成至少四个电介质层的叠层，并且用对第二和第四电介质层选择性的工艺蚀刻第一和第三电介质层，用对第一和第二电介质层选择的工艺蚀刻第二和第三电介质层。 有利地，用于蚀刻第三介电层的工艺对第一介电层基本不具有选择性。
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8.发明申请METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS 有权使用超深度VIAS制造超深度VIAS和三维集成电路的方法公开(公告)号：US20090068835A1
公开(公告)日：2009-03-12
申请号：US11853139
申请日：2007-09-11
IPC分类号： H01L21/311 , H01L21/44
CPC分类号： H01L27/0688 , H01L21/76804 , H01L21/76898 , H01L23/481 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
摘要翻译： 通过多个电介质层开口形成高纵横比的方法，高纵横比导电通孔，形成三维集成电路的方法和三维集成电路。 所述方法包括形成至少四个电介质层的叠层，并且用对第二和第四电介质层选择性的工艺蚀刻第一和第三电介质层，用对第一和第二电介质层选择的工艺蚀刻第二和第三电介质层。 有利地，用于蚀刻第三介电层的工艺对第一介电层基本不具有选择性。
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公开(公告)号：US08906248B2
公开(公告)日：2014-12-09
申请号：US13324895
申请日：2011-12-13
IPC分类号： H01L21/302 , H01L21/461 , H01L21/3213 , H01L21/311
CPC分类号： H01L21/32137 , H01L21/3065 , H01L21/3081 , H01L21/31116
摘要： A method etching features through a stack of a silicon nitride layer over a silicon layer over a silicon oxide layer in a plasma processing chamber is provided. The silicon nitride layer is etched in the plasma processing chamber, comprising; flowing a silicon nitride etch gas; forming the silicon nitride etch gas into a plasma to etch the silicon nitride layer, and stopping the flow of the silicon nitride etch gas. The silicon layer is, comprising flowing a silicon etch gas, wherein the silicon etch gas comprises SF6 or SiF4, forming the silicon etch gas into a, and stopping the flow of the silicon etch gas. The silicon oxide layer is etched in the plasma processing chamber, comprising flowing a silicon oxide etch gas, forming the silicon oxide etch gas into a plasma, and stopping the flow of the silicon oxide etch gas.
摘要翻译： 提供了通过在等离子体处理室中的硅氧化物层上的硅层上的氮化硅层的堆叠的方法蚀刻特征。 在等离子体处理室中蚀刻氮化硅层，包括： 流动氮化硅蚀刻气体; 将氮化硅蚀刻气体形成等离子体以蚀刻氮化硅层，并停止氮化硅蚀刻气体的流动。 硅层包括流动硅蚀刻气体，其中硅蚀刻气体包括SF 6或SiF 4，将硅蚀刻气体形成为硅并且阻止硅蚀刻气体的流动。 在等离子体处理室中蚀刻氧化硅层，包括使氧化硅蚀刻气体流动，将氧化硅蚀刻气体形成等离子体，并停止氧化硅蚀刻气体的流动。
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10.发明申请公开(公告)号：US20080277726A1
公开(公告)日：2008-11-13
申请号：US11745994
申请日：2007-05-08
申请人： Bruce B. Doris , Eduard Albert Cartier , Barry Paul Linder , Vijay Narayanan , Vamsi Paruchuri , Mark Todhunter Robson , Michelle L. Steen , Ying Zhang
发明人： Bruce B. Doris , Eduard Albert Cartier , Barry Paul Linder , Vijay Narayanan , Vamsi Paruchuri , Mark Todhunter Robson , Michelle L. Steen , Ying Zhang
IPC分类号： H01L27/01 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823807 , H01L21/823842 , H01L27/1203 , H01L29/7843 , H01L29/785
摘要： FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. As a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. The FET device structures further contain stressed device channels, and gates with effective workfunctions of n+ Si and p+ Si values.
摘要翻译： 公开了具有高k介质栅极绝缘体和含金属栅极的PFET和NFET器件的FET器件结构。 NFET和PFET器件中的栅极的金属层已经由单个公共金属层制造。 由于使用单层金属作为两种器件的栅极的结果，NFET和PFET的端子电极可以直接物理接触地彼此对接。 FET器件结构还包含受应力的器件通道，以及具有n + S和Si + Si值的有效功函数的栅极。
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