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公开(公告)号：US20230119518A1
公开(公告)日：2023-04-20
申请号：US17966463
申请日：2022-10-14
Inventor： Ja Yol LEE
Abstract: A phase-locked loop circuit includes a voltage controlled oscillator (VCO) that generates a VCO clock in response to a voltage control signal, a divider that divides the VCO clock to output a division clock, a phase-frequency error detector that receives a reference clock and outputs a first error compensation signal, a sampler that receives the reference clock and oversamples the reference clock at a rising edge or a falling edge to output a sampling clock, a window phase error detector that receives the reference clock and outputs a second error compensation signal, a residue phase error detector that outputs a third error compensation signal, an adder that accumulates the first error compensation signal, the second error compensation signal, and the third error compensation signal to output a final error compensation signal, and a loop filter that converts and output the final error compensation signal into the voltage control signal.
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公开(公告)号：US20160373121A1
公开(公告)日：2016-12-22
申请号：US15184113
申请日：2016-06-16
Inventor： Ja Yol LEE , Minjae LEE , Cheon Soo KIM , Jaehyun KANG , Minuk HEO
Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal. The phase locked loop (PLL) includes a divider configured to divide the output clock signal to generate a divided clock signal, a time-pulse converter configured to generate a time-pulse conversion signal that has a pulse corresponding to a phase difference between the reference clock signal and the divided clock signal, and a digitally controlled oscillator including an LC resonance circuit for generating the output clock signal and configured to control a frequency of the output clock signal that is determined to correspond to a time constant of the LC resonance circuit according to the time-pulse conversion signal, wherein a sustainment time of changed capacitance is continuously controlled according to a change in the phase difference between the reference clock signal and the divided clock signal.
Abstract translation: 提供了一种产生对应于参考时钟信号的输出时钟信号的锁相环（PLL）。 锁相环（PLL）包括分配器，其被配置为分频输出时钟信号以产生分频时钟信号;时间脉冲转换器，被配置为产生时间脉冲转换信号，该时间脉冲转换信号具有对应于参考的相位差的脉冲 时钟信号和分频时钟信号;以及数字控制振荡器，包括用于产生输出时钟信号的LC谐振电路，并且被配置为控制被确定为对应于LC谐振电路的时间常数的输出时钟信号的频率， 涉及时间脉冲转换信号，其中根据参考时钟信号和分频时钟信号之间的相位差的变化连续地控制改变的电容的维持时间。
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Patent Agency Ranking
公开(公告)号：US20180278072A1
公开(公告)日：2018-09-27
申请号：US15933853
申请日：2018-03-23
Inventor： Ja Yol LEE , Bon Tae KOO
Abstract: Provided is a battery charging system including a battery gauge configured to scale down to indicate a charging capacity of a battery, a charging mode switching unit configured to monitor a charging state of the battery gauge, switch a charging mode according to the charging state of the battery gauge, and charge the battery according to the switched charging mode, and a battery charging control unit configured to receive a charging current input to the battery gauge and a battery charging current input to the battery, and control the charging mode switching unit.
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公开(公告)号：US20160373115A1
公开(公告)日：2016-12-22
申请号：US15185438
申请日：2016-06-17
Inventor： Ja Yol LEE , Minjae LEE , Cheon Soo KIM , Jaehyun KANG , Junsoo KO
CPC classification number: H03K5/135 , H03K2005/00052 , H03L7/081 , H03L2207/50
Abstract: Provided is a phase locked loop (PLL) that generates an output clock signal corresponding to a reference clock signal, the PLL including a first phase interpolator configured to generate a first interpolator clock signal that has a first time delay from the output clock signal and a second phase interpolator configured to generate a second interpolator clock signal that has a second time delay from the output clock signal. The PLL controls a frequency of the output clock signal based on a multiplexing the first interpolator clock signal and the second interpolator clock signal.
Abstract translation: 提供了一种产生对应于参考时钟信号的输出时钟信号的锁相环（PLL），PLL包括第一相位内插器，其被配置为产生具有来自输出时钟信号的第一时间延迟的第一内插时钟信号，以及 第二相位插值器被配置为产生具有来自输出时钟信号的第二时间延迟的第二内插时钟信号。 基于多路复用第一内插时钟信号和第二内插时钟信号，PLL控制输出时钟信号的频率。
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5.发明申请公开(公告)号：US20180143296A1
公开(公告)日：2018-05-24
申请号：US15818667
申请日：2017-11-20
Inventor： Ja Yol LEE , Bon Tae KOO
CPC classification number: G01S7/35 , G01S13/343 , G01S13/345 , H03B5/04 , H03B5/32 , H03F3/19 , H03F3/21 , H03F2200/294 , H03F2200/451 , H03L1/02 , H03L7/089 , H03L7/0891 , H03L7/093 , H03L7/12
Abstract: Provided is frequency-modulated continuous wave generator. The frequency-modulated continuous wave generator includes a ramp signal generator configured to generate an analog ramp signal, a reference signal generator configured to generate a reference signal based on the analog ramp signal, a phase locked loop configured to output a control voltage based on the reference signal, and a voltage-controlled oscillator configured to generate a frequency-modulated continuous wave based on the control voltage. The ramp signal generator is further configured to generate the analog ramp signal based on a feedback signal based on the frequency-modulated continuous wave.
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公开(公告)号：US20170201259A1
公开(公告)日：2017-07-13
申请号：US15273764
申请日：2016-09-23
Inventor： Ja Yol LEE , Min Jae LEE , Cheon Soo KIM , Min Uk HEO
CPC classification number: H03L7/0991 , H03L7/081 , H03L7/085 , H03L7/091 , H03L7/093 , H03L7/18 , H03L7/183
Abstract: Provided herein is a digital PLL, which can minimize spurious noise. The digital PLL includes a digital controlled oscillator configured to generate an output oscillation signal in response to a digital code, a phase modulation unit configured to perform phase interpolation on the output oscillation signal in response to a phase control code, a TDC configured to generate an error code using a time difference between a reference clock signal and a modulated clock signal, an error detection unit configured to generate a delay code required to compensate for a phase shift error in response to the phase control code and the error code, a delay unit configured to delay at least one of the reference clock signal and the modulated clock signal and provide a delayed clock signal, and a first decoder configured to control the delay unit in response to the delay code.
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公开(公告)号：US20130214959A1
公开(公告)日：2013-08-22
申请号：US13743711
申请日：2013-01-17
Inventor： Ja Yol LEE
IPC: H03M1/50
CPC classification number: H03M1/50 , G04F10/005
Abstract: Disclosed is a low-power and high-resolution time-to-digital converter including: a coarse delay cell configured to delay a reference clock by a coarse delay time and output the reference clock; a rising-edge retimer configured to output a rising-edge retimed clock synchronized with the rising-edge of a DCO clock in response to the reference clock; a falling-edge retimer configured to output a falling-edge retimed clock synchronized with the falling-edge of the DCO clock; a firs sampler configured to latches output of the coarse delay cell in response to the rising-edge retimed clock and the falling-edge retimed clock; and a pseudo-thermometer code edge detector configured to detect a rising-edge fractional phase error between the reference clock and the rising-edge retimed clock as a coarse phase error from a signal output by the first sampler, and detect a falling-edge fractional phase error between the reference clock and the falling-edge retimed clock.
Abstract translation: 公开了一种低功率和高分辨率时间 - 数字转换器，包括：粗延迟单元，被配置为延迟参考时钟粗略延迟时间并输出参考时钟; 配置为响应于参考时钟输出与DCO时钟的上升沿同步的上升沿重新定时的上升沿重定时器; 配置成输出与DCO时钟的下降沿同步的下降沿重新定时的下降沿重定时器; 第一采样器被配置为响应于上升沿重新定时时钟和下降沿重新定时时钟来锁存粗延迟单元的输出; 以及伪温度计代码边缘检测器，被配置为从第一采样器输出的信号中检测参考时钟和上升沿重新定时时钟之间的上升沿分数相位误差作为粗略相位误差，并且检测下降沿分数 参考时钟和下降沿重新定时时钟之间的相位误差。
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