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公开(公告)号：US20140019656A1
公开(公告)日：2014-01-16
申请号：US14033008
申请日：2013-09-20
Applicant: Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F13/24
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system
Abstract translation: 控制多个不对称核心之间的功率和处理的技术。 在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程
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公开(公告)号：US20130318373A1
公开(公告)日：2013-11-28
申请号：US13954977
申请日：2013-07-31
Applicant: Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system
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公开(公告)号：US08930722B2
公开(公告)日：2015-01-06
申请号：US12380210
申请日：2009-02-25
Applicant: Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Eric Sprangle , Doug Carmean , Rajesh Kumar
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric processing elements are disclosed. In one embodiment, one or more asymmetric processing elements are power managed to migrate processes or threads among a plurality of processing elements according to the performance and power needs of the system.
Abstract translation: 公开了在多个不对称处理元件之间控制功率和处理的技术。 在一个实施例中，一个或多个非对称处理元件被功率管理以根据系统的性能和功率需求在多个处理元件之间迁移进程或线程。
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4.发明授权Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power state 有权在多核处理器中迁移不同指令集架构的内核之间的线程执行，并将每个内核转换为相应的开/关电源状态公开(公告)号：US08615647B2
公开(公告)日：2013-12-24
申请号：US12220092
申请日：2008-07-22
Applicant: Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/32
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
Abstract translation: 控制多个不对称核心之间的功率和处理的技术。 在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程。
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公开(公告)号：US20140130058A1
公开(公告)日：2014-05-08
申请号：US14154517
申请日：2014-01-14
Applicant: Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F9/50
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
Abstract translation: 控制多个不对称核心之间的功率和处理的技术。 在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程。
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Patent Agency Ranking
公开(公告)号：US20130318374A1
公开(公告)日：2013-11-28
申请号：US13954980
申请日：2013-07-31
Applicant: Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06F1/32
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system
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公开(公告)号：US20130314425A1
公开(公告)日：2013-11-28
申请号：US13954979
申请日：2013-07-31
Applicant: Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
IPC: G06T1/20
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system
Abstract translation: 控制多个不对称核心之间的功率和处理的技术。 在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程
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公开(公告)号：US20100005474A1
公开(公告)日：2010-01-07
申请号：US12380210
申请日：2009-02-25
Applicant: Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Eric Sprangle , Doug Carmean , Rajesh Kumar
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: A technique to promote determinism among multiple clocking domains within a computer system or integrated circuit. In one embodiment, one or more execution units are placed in a deterministic state with respect to multiple clocks within a processor system having a number of different clocking domains.
Abstract translation: 一种促进计算机系统或集成电路内多个时钟域之间确定性的技术。 在一个实施例中，一个或多个执行单元相对于具有多个不同计时域的处理器系统内的多个时钟被置于确定性状态。
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公开(公告)号：US20090222654A1
公开(公告)日：2009-09-03
申请号：US12220092
申请日：2008-07-22
Applicant: Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
Inventor： Herbert Hum , Eric Sprangle , Doug Carmean , Rajesh Kumar
CPC classification number: G06F1/3293 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/3228 , G06F1/324 , G06F1/3287 , G06F1/3296 , G06F9/3869 , G06F9/461 , G06F9/5088 , G06F9/5094 , G06F12/0875 , G06F13/24 , G06F2209/5017 , G06F2212/452 , G06T1/20 , Y02B70/10 , Y02B70/1425 , Y02B70/30 , Y02B70/32 , Y02D10/122 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.
Abstract translation: 控制多个不对称核心之间的功率和处理的技术。 在一个实施例中，根据系统的性能和功率需求，一个或多个非对称核被功率管理以在多个核之间迁移进程或线程。
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公开(公告)号：US10685947B2
公开(公告)日：2020-06-16
申请号：US15869637
申请日：2018-01-12
Applicant: Wilfred Gomes , Mark T. Bohr , Rajesh Kumar , Robert L. Sankman , Ravindranath V. Mahajan , Wesley D. Mc Cullough
Inventor： Wilfred Gomes , Mark T. Bohr , Rajesh Kumar , Robert L. Sankman , Ravindranath V. Mahajan , Wesley D. Mc Cullough
IPC: H01L23/48 , H01L25/18 , H01L25/00 , H01L23/00 , H01L23/538 , H01L23/522 , H01L25/16 , H01L25/065 , H01L23/498
Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.
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