公开(公告)号：US10128187B2

公开(公告)日：2018-11-13

申请号：US15206361

申请日：2016-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts

IPC: H01L21/70 ,  H01L23/528 ,  H01L21/768 ,  H01L23/535 ,  H01L23/66 ,  H01L29/06 ,  H01L29/78

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; a conductor extending above, without contacting, the source/drain contact and extending within the dielectric layer to contact the gate conductor within the gate stack.

公开(公告)号：US10090209B2

公开(公告)日：2018-10-02

申请号：US15615072

申请日：2017-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Amit A. Dikshit ,  Tamilmani Ethirajan ,  Shrinivas J. Pandharpure ,  Vaidyanathan T. Subramanian ,  Josef S. Watts

IPC: H01G7/00 ,  H01L21/66 ,  G06F17/50 ,  G01R31/26

Abstract: Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (fT) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (Vd1); extracting a transconductance (Gm) from the first set of in-line DC parameters as a function of a gate-voltage (Vg) and the first drain-voltage (Vd1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (Vd2); extracting a total gate capacitance (Cgg) from the second set of in-line DC parameters as a function of the gate-voltage (Vg); and predicting the unity gain frequency (fT) of the MOSFET based upon the extracted transconductance (Gm) and the extracted total gate capacitance (Cgg).

公开(公告)号：US10170473B1

公开(公告)日：2019-01-01

申请号：US15811745

申请日：2017-11-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Yi Qi

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L21/266 ,  H01L29/66 ,  H01L29/06

Abstract: A method of forming an integrated circuit includes forming a FinFET by: forming a semiconductor fin on a semiconductor substrate; forming a first source/drain region in the semiconductor substrate under a first end of the semiconductor fin and a second source/drain region in the semiconductor substrate under a second, opposing end of the semiconductor fin, the second source/drain region separated from the first source/drain region by a portion of the semiconductor substrate having an opposite doping from that of the first and second source/drain region; and forming a surrounding gate extending about the semiconductor fin above the semiconductor substrate. A second vertical FinFET may be formed simultaneously. The method allows the FinFET to have a long channel extending laterally through its fin compared to the short channel of the vertical FinFET, thus creating short channel and long channel devices together without impacting vertical FinFET height.

公开(公告)号：US20180083089A1

公开(公告)日：2018-03-22

申请号：US15271730

申请日：2016-09-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Shesh M. Pandey

IPC: H01L49/02 ,  H01L21/3205 ,  H01L21/02 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L21/02164 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02595 ,  H01L21/32055 ,  H01L27/0629

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

公开(公告)号：US09405186B1

公开(公告)日：2016-08-02

申请号：US14628446

申请日：2015-02-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Amr Y. Abdo ,  Nathalie Casati ,  Maria Gabrani ,  James M. Oberschmidt ,  Ramya Viswanathan ,  Josef S. Watts

IPC: G06F17/50 ,  G03F1/36

CPC classification number: G03F1/36 ,  G06F17/5081

Abstract: Methods, program products, and systems for improving optical proximity correction (OPC) calibration, and automatically determining a minimal number of clips, are disclosed. The method can include using a computing device to perform actions including: calculating a total relevancy score for a projected sample plan including a candidate clip, and wherein the relevancy score is derived from at least one relevancy criterion and a relevancy weight; calculating a relevancy score for the candidate clip, the relevancy score for the candidate clip being a contribution from the candidate clip to the total relevancy score; and adding the candidate clip to a sample plan for the IC layout and removing the candidate clip from the plurality of clips in response a difference in relevancy score between the projected sample plan and one or more previous sample plans substantially fitting a non-linear relevancy score function.

Abstract translation: 公开了用于改进光学邻近校正（OPC）校准以及自动确定最小数量的片段的方法，程序产品和系统。 该方法可以包括使用计算设备来执行动作，包括：计算包括候选剪辑的投影样本计划的总相关性得分，并且其中所述相关性得分来自至少一个相关性标准和相关权重; 计算候选剪辑的相关性分数，候选剪辑的相关性分数是从候选剪辑到总相关性分数的贡献; 以及将所述候选剪辑添加到所述IC布局的样本计划并从所述多个剪辑中移除所述候选剪辑，以响应所述预测样本计划与基本拟合非线性相关性得分的一个或多个先前样本计划之间的相关性得分的差异 功能。

公开(公告)号：US10079308B1

公开(公告)日：2018-09-18

申请号：US15682631

申请日：2017-08-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shesh Mani Pandey ,  Hui Zang ,  Josef S. Watts

IPC: H01L21/70 ,  H01L29/786 ,  H01L21/768 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/78642 ,  H01L21/76829 ,  H01L21/823412 ,  H01L29/66643 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833

Abstract: The disclosure provides a vertical FinFET structure, including: a substrate including a first source/drain region; a looped channel region positioned on the first source/drain region of the substrate, the looped channel region having an inner perimeter which surrounds a hollow interior of the looped channel region; a first gate positioned within the hollow interior of the looped channel region, wherein the first gate is formed onto the looped channel region along the inner perimeter of the looped channel region; and a second source/drain region positioned on and overlying an upper surface of the looped channel region.

公开(公告)号：US20180012839A1

公开(公告)日：2018-01-11

申请号：US15206361

申请日：2016-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/66 ,  H01L23/535 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L23/5283 ,  H01L21/76805 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/535 ,  H01L23/66 ,  H01L29/0653 ,  H01L29/785

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; a conductor extending above, without contacting, the source/drain contact and extending within the dielectric layer to contact the gate conductor within the gate stack.

公开(公告)号：US10374029B2

公开(公告)日：2019-08-06

申请号：US15848324

申请日：2017-12-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts ,  Shesh M. Pandey

IPC: H01L49/02 ,  H01L21/02 ,  H01L21/3205 ,  H01L27/06

Abstract: A resistor body is separated from a doped well in a substrate by a resistor dielectric material layer. The doped well is defined by at least one doped region and can include a dopant gradient in the doped well to reduce parasitic capacitance of the resistor structure while retaining heat dissipation properties of the substrate. The resistor body is formed in a cavity in a dielectric layer deposited on the substrate, which deposition can be part of a concurrent fabrication, such as part of forming shallow trench isolations, and the cavity can be lined with the resistor dielectric material.

公开(公告)号：US20190006280A1

公开(公告)日：2019-01-03

申请号：US16122259

申请日：2018-09-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Josef S. Watts

IPC: H01L23/528 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535 ,  H01L23/66 ,  H01L29/06

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate stack having a gate conductor therein over a substrate, the gate stack being within a dielectric layer; a source/drain contact to a source/drain region over the substrate and adjacent to the gate stack within the dielectric layer; an upper conductor extending above, without contacting, the source/drain contact, wherein the upper conductor extends within the dielectric layer to contact the gate conductor within the gate stack.

公开(公告)号：US20170271213A1

公开(公告)日：2017-09-21

申请号：US15615072

申请日：2017-06-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Amit A. Dikshit ,  Tamilmani Ethirajan ,  Shrinivas J. Pandharpure ,  Vaidyanathan T. Subramanian ,  Josef S. Watts

IPC: H01L21/66 ,  G06F17/50

CPC classification number: H01L22/14 ,  G01R31/2621 ,  G01R31/2625 ,  G06F17/5036 ,  G06F17/5063

Abstract: Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency (fT) in a MOSFET device in a manufacturing line, the method including: measuring a first set of in-line direct current (DC) parameters of the MOSFET on the manufacturing line at a first drain voltage (Vd1); extracting a transconductance (Gm) from the first set of in-line DC parameters as a function of a gate-voltage (Vg) and the first drain-voltage (Vd1); measuring a second set of in-line DC parameters of the MOSFET on the manufacturing line at a second drain voltage (Vd2); extracting a total gate capacitance (Cgg) from the second set of in-line DC parameters as a function of the gate-voltage (Vg); and predicting the unity gain frequency (fT) of the MOSFET based upon the extracted transconductance (Gm) and the extracted total gate capacitance (Cgg).