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    FinFET channel stress using tungsten contacts in raised epitaxial source and drain
    1.
    发明授权
    FinFET channel stress using tungsten contacts in raised epitaxial source and drain 有权
    FinFET沟道应力使用钨触点在凸起的外延源和漏极中

    公开(公告)号：US08975142B2

    公开(公告)日：2015-03-10

    申请号：US13870854

    申请日：2013-04-25

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Abhijeet Paul ,  Abner Bello ,  Vimal K. Kamineni ,  Derya Deniz

    IPC: H01L29/786 ,  H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/8238

    CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/785

    Abstract: Performance of a FinFET is enhanced through a structure that exerts physical stress on the channel. The stress is achieved by a combination of tungsten contacts for the source and drain, epitaxially grown raised source and raised drain, and manipulation of aspects of the tungsten contact deposition resulting in enhancement of the inherent stress of tungsten. The stress can further be enhanced by epitaxially re-growing the portion of the raised source and drain removed by etching trenches for the contacts and/or etching deeper trenches (and corresponding longer contacts) below a surface of the fin.

    Abstract translation: 通过在通道上施加物理应力的结构来增强FinFET的性能。 应力通过用于源极和漏极的钨触点，外延生长的升高源和升高的漏极的组合以及钨接触沉积的方面的操作来实现，从而导致钨的固有应力的增强。 通过外延重新生长升高的源极和漏极的部分，通过蚀刻用于触点的沟槽和/或蚀刻在鳍的表面下方的较深的沟槽（和相应的更长的触点）来进一步增强应力。

    Methods of forming stressed fin channel structures for FinFET semiconductor devices
    2.
    发明授权
    Methods of forming stressed fin channel structures for FinFET semiconductor devices 有权
    形成用于FinFET半导体器件的应力鳍式通道结构的方法

    公开(公告)号：US09117930B2

    公开(公告)日：2015-08-25

    申请号：US13960200

    申请日：2013-08-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, Jr.

    IPC: H01L21/8234 ,  H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

    Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

    Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。

    METHODS OF FORMING STRESSED FIN CHANNEL STRUCTURES FOR FINFET SEMICONDUCTOR DEVICES
    3.
    发明申请
    METHODS OF FORMING STRESSED FIN CHANNEL STRUCTURES FOR FINFET SEMICONDUCTOR DEVICES 有权
    为FINFET半导体器件形成应力FIN通道结构的方法

    公开(公告)号：US20150041906A1

    公开(公告)日：2015-02-12

    申请号：US13960200

    申请日：2013-08-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, JR.

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0924

    Abstract: One method disclosed herein includes forming a first stressed conductive layer within the trenches of a FinFET device and above the upper surface of a fin, forming a second stressed conductive layer above the first stressed conductive layer, removing a portion of the second stressed conductive layer and a portion of the first stressed conductive layer that is positioned above the fin while leaving portions of the first stressed conductive layer positioned within the trenches, and forming a conductive layer above the second stressed conductive layer, the upper surface of the fin and the portions of the first stressed conductive layer positioned within the trenches.

    Abstract translation: 本文公开的一种方法包括在FinFET器件的沟槽内并在鳍的上表面上方形成第一应力导电层，在第一应力导电层上形成第二应力导电层，去除第二应力导电层的一部分， 所述第一应力导电层的位于所述鳍片上方的部分，同时留下位于所述沟槽内的所述第一应力导电层的部分，并且在所述第二应力导电层上方形成导电层，所述翅片的上表面和 第一应力导电层位于沟槽内。

    Methods and systems for chemical mechanical planarization endpoint detection using an alternating current reference signal
    4.
    发明授权
    Methods and systems for chemical mechanical planarization endpoint detection using an alternating current reference signal 有权

    公开(公告)号：US10343253B2

    公开(公告)日：2019-07-09

    申请号：US14311761

    申请日：2014-06-23

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Abner Bello ,  Michael Wedlake

    IPC: B24B37/04 ,  B24B37/27 ,  B24B37/005

    Abstract: Methods, non-transitory computer readable media, and systems are provided for detecting an endpoint of a chemical mechanical planarization (CMP) process on a semiconductor substrate. The method comprises generating a reference signal, generating a first signal with which to control a CMP system, generating a second signal using a combination of the first signal and the reference signal, commanding the CMP system with the second signal, generating a response signal that indicates an operational characteristic of the CMP system that is responsive to the second signal and a friction property of the semiconductor substrate, and filtering the response signal using the reference signal to determine the endpoint of the CMP process.

    Methods of forming stressed fin channel structures for FinFET semiconductor devices
    7.
    发明授权
    Methods of forming stressed fin channel structures for FinFET semiconductor devices 有权
    形成用于FinFET半导体器件的应力鳍式通道结构的方法

    公开(公告)号：US08889500B1

    公开(公告)日：2014-11-18

    申请号：US13960244

    申请日：2013-08-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Vimal K. Kamineni ,  Derya Deniz ,  Abner Bello ,  Abhijeet Paul ,  Robert J. Miller ,  William J. Taylor, Jr.

    IPC: H01L21/338 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/66795 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/785

    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of fin-formation trenches that define a fin, forming a first stressed layer within the trenches and above the fin and performing at least one etching process on the first stressed layer so as to define spaced-apart portions of the first stressed layer positioned at least partially within the trenches on opposite sides of the fin. The method also includes forming spaced-apart portions of a second stressed layer above the spaced-apart portions of the first layer, forming a third stressed layer above the fin between the spaced-apart portions of the second layer and, after forming the third layer, forming a conductive layer above the second and third layers.

    Abstract translation: 本文公开的一种说明性方法包括形成限定翅片的多个翅片形成沟槽，在沟槽内和翅片上方形成第一应力层，并在第一应力层上执行至少一个蚀刻工艺，以便 以限定至少部分地位于鳍片的相对侧上的沟槽内的第一应力层的间隔开的部分。 该方法还包括在第一层的间隔开的部分上方形成第二应力层的间隔开的部分，在第二层间隔开的部分之间形成翅片之上的第三应力层，在形成第三层之后 在第二层和第三层上形成导电层。

    Rechargeable wafer carrier systems
    8.
    发明授权
    Rechargeable wafer carrier systems 有权

    公开(公告)号：US10931143B2

    公开(公告)日：2021-02-23

    申请号：US15233454

    申请日：2016-08-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Abner Bello ,  Stephanie Waite ,  William J. Fosnight

    IPC: H02J50/10 ,  H02J7/00 ,  H02J7/02 ,  H01L21/677 ,  H01L21/673

    Abstract: Rechargeable wafer carrier systems and methods are provided. A rechargeable wafer carrier system includes, for instance, a housing for holding at least one wafer and at least one electronics system therein, a rechargeable power source operably connected to the housing for powering the at least one electronics system, and a charging interface for receiving a supply of power for charging the rechargeable power source. The housing may be configured for transport within an automated material handling system. Also provided are methods of charging a rechargeable wafer carrier system, which includes, for instance, providing a rechargeable wafer carrier system having at least one electronics system and a rechargeable power source, operably connecting the rechargeable wafer carrier system to a charging base, and supplying power from the charging base to the rechargeable power source.

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