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    Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails
    1.
    发明授权
    Method of reducing fin width in FinFET SRAM array to mitigate low voltage strap bit fails 有权

    公开(公告)号：US10163914B2

    公开(公告)日：2018-12-25

    申请号：US15603827

    申请日：2017-05-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiaoqiang Zhang ,  Hui Zang ,  Ratheesh R. Thankalekshmi ,  Randy W. Mann

    IPC: H01L29/66 ,  H01L27/11

    Abstract: A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process.

    Cross couple structure for vertical transistors
    3.
    发明授权
    Cross couple structure for vertical transistors 有权

    公开(公告)号：US10109637B1

    公开(公告)日：2018-10-23

    申请号：US15856205

    申请日：2017-12-28

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hui Zang ,  Randy W. Mann ,  Bipul C. Paul

    IPC: H01L27/11 ,  H01L23/528 ,  H01L23/522 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45

    Abstract: The disclosure provides integrated circuit (IC) structure including: a substrate; a shallow trench isolation (STI) positioned between the first and second regions of the substrate; a first transistor with a channel region is positioned on the first region of the substrate, and spacer positioned on the first region of the substrate and the STI; and a gate metal positioned on the spacer. The gate metal includes a gate contact region positioned over the first source/drain region of the substrate, and surrounding the channel region. Across-couple region extends laterally from the gate contact region to the source/drain region of a second transistor formed on the second region of the substrate.

    Integrated circuit with semiconductor fin fuse
    5.
    发明授权
    Integrated circuit with semiconductor fin fuse 有权
    集成电路与半导体鳍片保险丝

    公开(公告)号：US09219040B2

    公开(公告)日：2015-12-22

    申请号：US14032484

    申请日：2013-09-20

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Randy W. Mann ,  Kingsuk Maitra ,  Anurag Mittal

    IPC: H01L23/525 ,  H01L23/62

    CPC classification number: H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.

    Abstract translation: 提供了制造具有鳍式保险丝的集成电路的方法，以及所得到的具有鳍式保险丝的集成电路。 在该方法中，由半导体材料层产生翅片并具有第一端和第二端。 该方法提供了在翅片上从其第一端到其第二端形成导电路径。 导电路径电连接到编程设备，该编程设备能够选择性地将编程电流引导通过导电路径，从而导致导电路径中的结构变化，以增加穿过导电路径的电阻。

    STRUCTURES AND SRAM BIT CELLS INTEGRATING COMPLEMENTARY FIELD-EFFECT TRANSISTORS
    6.
    发明申请
    STRUCTURES AND SRAM BIT CELLS INTEGRATING COMPLEMENTARY FIELD-EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20200286900A1

    公开(公告)日：2020-09-10

    申请号：US16295485

    申请日：2019-03-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Randy W. Mann ,  Bipul C. Paul ,  Julien Frougier ,  Ruilong Xie

    IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

    Abstract: Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

    STATIC RANDOM ACCESS MEMORY CELLS WITH ARRANGED VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS
    7.
    发明申请
    STATIC RANDOM ACCESS MEMORY CELLS WITH ARRANGED VERTICAL-TRANSPORT FIELD-EFFECT TRANSISTORS 审中-公开

    公开(公告)号：US20190355730A1

    公开(公告)日：2019-11-21

    申请号：US15983627

    申请日：2018-05-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Randy W. Mann ,  Bipul C. Paul

    IPC: H01L27/11

    Abstract: Structures for a static random access memory (SRAM) bitcell and methods for forming a SRAM bitcell. The SRAM includes a storage element with a first pull-up (PU) vertical-transport field-effect transistor (VTFET) having a first bottom source/drain region and a fin projecting from the first bottom source/drain region, and a second pull-up (PU) VTFET with a second bottom source/drain region and a fin projecting from the second bottom source/drain region. The fin of the first PU VTFET is arranged over a first active region in which the first bottom source/drain region is centrally arranged, and the fin of the second PU VTFET is arranged over a second active region in which the second bottom source/drain region is centrally arranged. The second source/drain region is aligned with the first bottom source/drain region. A read port may be connected with the storage element, and may also be formed using VTFETs.

    Six-transistor (6T) SRAM cell structure
    8.
    发明授权
    Six-transistor (6T) SRAM cell structure 有权

    公开(公告)号：US10403629B2

    公开(公告)日：2019-09-03

    申请号：US15804556

    申请日：2017-11-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Randy W. Mann ,  Bipul C. Paul

    IPC: H01L27/11 ,  H01L27/092 ,  G11C11/412 ,  H01L27/118

    Abstract: One illustrative 6T SRAM cell structure disclosed herein includes a first active region with a first N-type pass gate transistor, a first N-type pull-down transistor and a first P-type pull-up transistor, each of which are formed in and above the first active region, wherein the first N-type pull-down transistor is positioned laterally between the first N-type pass gate transistor and the first P-type pull-up transistor, and a second active region with a second N-type pass gate transistor, a second N-type pull-down transistor and a second P-type pull-up transistor, each of which are formed in and above the second active region, wherein the second N-type pull-down transistor is positioned laterally between the second N-type pass gate transistor and the second P-type pull-up transistor.

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