公开(公告)号：US09922929B1

公开(公告)日：2018-03-20

申请号：US15363513

申请日：2016-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Roderick A. Augur ,  Hoon Kim

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53257 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self aligned interconnect structures and methods of manufacture. The structure includes an interconnect structure which is self-aligned with an upper level via metallization, and both the interconnect structure and the upper level via metallization are composed of a Pt group material.

公开(公告)号：US20200035495A1

公开(公告)日：2020-01-30

申请号：US16045111

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dewei Xu ,  Lili Cheng ,  Shinichiro Kakita ,  Ushasree Katakamsetty ,  Roderick A. Augur

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/67 ,  B24B37/005

Abstract: Apparatus and methods of chemical-mechanical polishing of a layer on a wafer. A plurality of polishers arranged on a rotating plate, and a carrier is configured to hold the wafer and to place the layer in contact with the polishers. Each polisher includes a platen and a force-applying device operatively connected to the platen, and the force-applying device is configured to apply a variable force to the platen in order to change a rate of material removal over an area of the layer on the wafer contacted by a polishing pad carried by the platen.

公开(公告)号：US20190148072A1

公开(公告)日：2019-05-16

申请号：US15815308

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Lili Cheng ,  Roderick A. Augur

IPC: H01G4/30 ,  H01G4/005 ,  H01G4/252

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.

公开(公告)号：US20160104670A1

公开(公告)日：2016-04-14

申请号：US14511344

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roderick A. Augur ,  Christian Witt

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76834 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/53204 ,  H01L23/53271 ,  H01L23/53276 ,  H01L23/53295 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a ballistic conductor line above a first metallization layer. A dielectric layer is formed above the ballistic conductor line. A first via is embedded in the dielectric layer contacting a first portion of the ballistic conductor line. A second via is embedded in the dielectric layer contacting a second portion of the ballistic conductor line to define a signal path between the first and second vias through the ballistic conductor line.

Abstract translation: 一种方法包括在第一金属化层之上形成弹道导体线。 在弹道导线之上形成电介质层。 第一通孔嵌入到接触弹道导体线的第一部分的电介质层中。 第二通孔嵌入在接触弹道导体线的第二部分的电介质层中，以通过弹道导线确定第一和第二通孔之间的信号路径。

公开(公告)号：US10199264B2

公开(公告)日：2019-02-05

申请号：US15875212

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Roderick A. Augur ,  Hoon Kim

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned interconnect structures and methods of manufacture. The structure includes an interconnect structure which is self-aligned with an upper level via metallization, and both the interconnect structure and the upper level via metallization are composed of a Pt group material.

公开(公告)号：US20180315707A1

公开(公告)日：2018-11-01

申请号：US15498083

申请日：2017-04-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Kevin M. Boyd ,  Nicholas A. Polomoff ,  Roderick A. Augur ,  Jeannine M. Trewhella

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/562

Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.

公开(公告)号：US20160104672A1

公开(公告)日：2016-04-14

申请号：US14511524

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roderick A. Augur ,  Christian Witt

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L21/76834 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76885 ,  H01L23/53204 ,  H01L23/53271 ,  H01L23/53276 ,  H01L23/53295 ,  H01L2221/1094 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of electrically connecting first and second conductive features includes forming a first metallization layer including the first conductive feature. A ballistic conductor line is formed above the first metallization layer. The ballistic conductor line contacts the first conductive feature proximate a first end of the ballistic conductor line. The second conductive feature is contacted proximate a second end of the ballistic conductor line.

Abstract translation: 电连接第一和第二导电特征的方法包括形成包括第一导电特征的第一金属化层。 在第一金属化层之上形成弹道导线。 弹道导线在靠近弹道导线的第一端接触第一导电特征。 第二导电特征在弹道导线的第二端附近接触。

公开(公告)号：US10580581B2

公开(公告)日：2020-03-03

申请号：US15815308

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Lili Cheng ,  Roderick A. Augur

IPC: H01G4/30 ,  H01G4/252 ,  H01G4/005 ,  H01G4/12 ,  H01L49/02 ,  H01G4/012 ,  H01G4/33 ,  H01G4/232

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.

公开(公告)号：US10153232B2

公开(公告)日：2018-12-11

申请号：US15498083

申请日：2017-04-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Kevin M. Boyd ,  Nicholas A. Polomoff ,  Roderick A. Augur ,  Jeannine M. Trewhella

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.

公开(公告)号：US09864132B1

公开(公告)日：2018-01-09

申请号：US15282320

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Roderick A. Augur ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B6/12 ,  H01L23/373 ,  H01L27/092

CPC classification number: G02B6/12 ,  G02B2006/12061 ,  G02B2006/12135 ,  H01L23/373 ,  H01L23/3733 ,  H01L23/3738 ,  H01L27/092

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon waveguide devices in integrated photonics and methods of manufacture. The integrated photonics structure includes: a localized region of negative thermal expansion (NTE) coefficient material formed within a trench; at least one photonics or CMOS component contacting with the negative thermal expansion (NTE) coefficient material; and cladding material formed above the at least one photonics or CMOS component.