公开(公告)号：US09633857B1

公开(公告)日：2017-04-25

申请号：US15087392

申请日：2016-03-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Steffen Sichler

IPC: H01L21/28 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/51 ,  H01L23/535 ,  H01L21/84 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L29/0649 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor structure includes a trench isolation structure, a trench capping layer, a gate structure and a sidewall spacer. The trench isolation structure includes a first electrically insulating material. The trench capping layer is provided over the trench isolation structure. The trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The gate structure includes a gate insulation layer including a high-k material and a gate electrode over the gate insulation layer. The gate structure has a first portion over the trench capping layer. The sidewall spacer is provided adjacent the gate structure. A portion of the sidewall spacer is provided on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer.

公开(公告)号：US10103224B2

公开(公告)日：2018-10-16

申请号：US15457384

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Steffen Sichler

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/51 ,  H01L29/49 ,  H01L29/08 ,  H01L23/535

Abstract: A semiconductor structure includes a trench isolation structure and a trench capping layer positioned over the trench isolation structure, wherein the trench isolation layer includes a first electrically insulating material and the trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The semiconductor structure also includes a gate structure having a gate insulation layer and a gate electrode positioned over the gate insulation layer, wherein the gate insulation layer includes a high-k material and the gate structure includes a first portion that is positioned over the trench capping layer. A sidewall spacer is positioned adjacent to the gate structure, wherein a portion of the sidewall spacer is positioned on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer.

公开(公告)号：US09876111B2

公开(公告)日：2018-01-23

申请号：US15091020

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steffen Sichler ,  Peter Javorka ,  Juergen Faul ,  Sylvain Henri Baudot ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7831

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.

公开(公告)号：US20170288015A1

公开(公告)日：2017-10-05

申请号：US15457384

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Steffen Sichler

IPC: H01L29/06 ,  H01L23/535 ,  H01L29/49 ,  H01L29/08 ,  H01L27/12 ,  H01L29/51

CPC classification number: H01L29/0649 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823475 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/517 ,  H01L29/66545

Abstract: A semiconductor structure includes a trench isolation structure and a trench capping layer positioned over the trench isolation structure, wherein the trench isolation layer includes a first electrically insulating material and the trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The semiconductor structure also includes a gate structure having a gate insulation layer and a gate electrode positioned over the gate insulation layer, wherein the gate insulation layer includes a high-k material and the gate structure includes a first portion that is positioned over the trench capping layer. A sidewall spacer is positioned adjacent to the gate structure, wherein a portion of the sidewall spacer is positioned on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer.

公开(公告)号：US20170170317A1

公开(公告)日：2017-06-15

申请号：US15091020

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steffen Sichler ,  Peter Javorka ,  Juergen Faul ,  Sylvain Henri Baudot ,  Thorsten Kammler

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L21/823418 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/66484 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7831

Abstract: A method of forming a semiconductor device structure is disclosed including providing a first active region and a second active region in an upper surface portion of a substrate, the first and second active regions being laterally separated by at least one isolation structure, forming a first gate structure comprising a first gate dielectric and a first gate electrode material over the first active region, and a second gate structure comprising a second gate dielectric and a second gate electrode material over the second active region, wherein a thickness of the second gate dielectric is greater than the thickness of the first gate dielectric, and forming a first sidewall spacer structure to the first gate structure and a second sidewall spacer structure to the second gate structure, wherein a lateral thickness of the second sidewall spacer structure is greater than a lateral thickness of the first sidewall spacer structure.