公开(公告)号：US20160190302A1

公开(公告)日：2016-06-30

申请号：US14585742

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/06 ,  H01L29/167 ,  H01L21/84 ,  H01L21/02 ,  H01L21/322 ,  H01L21/324 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

Abstract translation: 一种制造半导体器件的方法，其中：（i）所述散热片形成在多孔半导体材料层（例如，硅层）上; 和（ii）然后氧化多孔半导体层以形成绝缘体层（例如，SiO 2掩埋氧化物层）。 多孔半导体层中的孔促进了绝缘体层的可靠氧化，允许气态氧（O 2）在整个层中被氧化以形成绝缘体层。 在这些实施例的一些中，薄的无孔半导体层位于多孔半导体层之上（在其氧化之前），以允许材料的应变外延生长用于制造成品半导体器件的源极区域和漏极区域（用于 例如，FINFET）。

公开(公告)号：US09236271B2

公开(公告)日：2016-01-12

申请号：US13749330

申请日：2013-01-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Can Bayram ,  Stephen W. Bedell ,  Devendra K. Sadana ,  Katherine L. Saenger

IPC: H01L21/30 ,  H01L21/46 ,  H01L21/428 ,  H01L21/18 ,  H01L33/00 ,  H01L21/683

CPC classification number: H01L21/428 ,  H01L21/18 ,  H01L21/185 ,  H01L21/6835 ,  H01L21/6836 ,  H01L33/0079 ,  H01L2221/68368 ,  H01L2221/68381 ,  H01L2221/68386

Abstract: A pulsed laser-initiated exfoliation method for patterning a Group III-nitride film on a growth substrate is provided. This method includes providing a Group III-nitride film a growth substrate, wherein a growth substrate/Group III-nitride film interface is present between the Group III-nitride film and the growth substrate. Next, a laser is selected that provides radiation at a wavelength at which the Group III-nitride film is transparent and the growth substrate is absorbing. The interface is then irradiated with pulsed laser radiation from the Group III-nitride film side of the growth substrate/Group III-nitride film interface to exfoliate a region of the Group III-nitride from the growth substrate. A method for transfer a Group-III nitride film from a growth substrate to a handle substrate is also provided.

Abstract translation: 提供了用于在生长衬底上图案化III族氮化物膜的脉冲激光起始剥离方法。 该方法包括提供III族氮化物膜生长衬底，其中在III族氮化物膜和生长衬底之间存在生长衬底/ III族氮化物膜界面。 接下来，选择提供在III族氮化物膜透明并且生长衬底吸收的波长处的辐射的激光。 然后用生长衬底/ III族氮化物膜界面的III族氮化物膜侧的脉冲激光辐射照射该界面，以从生长衬底剥离III族氮化物的区域。 还提供了将III族氮化物膜从生长衬底转移到手柄衬底的方法。

公开(公告)号：US09368420B2

公开(公告)日：2016-06-14

申请号：US14732689

申请日：2015-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephen W. Bedell ,  Wilfried E. Haensch ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/01 ,  H01L23/14 ,  H01L27/12 ,  H01L27/092 ,  H01L23/538 ,  H01L21/762

CPC classification number: H01L23/14 ,  H01L21/4846 ,  H01L21/7624 ,  H01L23/5381 ,  H01L23/5386 ,  H01L23/5387 ,  H01L27/092 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Fabrication methods are disclosed that facilitate the production of electronic structures that are both flexible and stretchable to conform to non-planar (e.g. curved) surfaces without suffering functional damage due to excessive strain. Electronic structures including CMOS devices are provided that can be stretched or squeezed within acceptable limits without failing or breaking. The methods disclosed herein further facilitate the production of flexible, stretchable electronic structures having multiple levels of intra-chip connectors. Such connectors are formed through deposition and photolithographic patterning (back end of the line processing) and can be released following transfer of the electronic structures to flexible substrates.

公开(公告)号：US09224755B2

公开(公告)日：2015-12-29

申请号：US14020098

申请日：2013-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L21/00 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L27/3262 ,  H01L21/7624 ,  H01L21/76254 ,  H01L27/1218 ,  H01L27/1262 ,  H01L27/1266 ,  H01L27/3248 ,  H01L51/5218 ,  H01L51/5221 ,  H01L51/5237 ,  H01L2227/323 ,  H01L2227/326 ,  H01L2251/5338

Abstract: High resolution active matrix structures are fabricated using techniques applicable to flexible substrates. A backplane layer including active semiconductor devices is formed using a semiconductor-on-insulator substrate. The substrate is thinned using a layer transfer technique or chemical/mechanical processing. Driver transistors are formed on the semiconductor layer of the substrate along with additional circuits that provide other functions such as computing or sensing. Contacts to passive devices such as organic light emitting diodes may be provided by heavily doped regions formed in the handle layer of the substrate and then isolated. A gate dielectric layer may be formed on the semiconductor layer, which functions as a channel layer, or the insulator layer of the substrate may be employed as a gate dielectric layer.

Abstract translation: 使用适用于柔性基板的技术制造高分辨率有源矩阵结构。 包括有源半导体器件的背板层使用绝缘体上半导体衬底形成。 使用层转移技术或化学/机械加工使衬底变薄。 在衬底的半导体层上形成驱动晶体管以及提供计算或感测等其它功能的附加电路。 与诸如有机发光二极管的无源器件的接触可以由形成在衬底的手柄层中的重掺杂区域提供，然后被隔离。 可以在用作沟道层的半导体层上形成栅极电介质层，或者可以将衬底的绝缘体层用作栅极介电层。

公开(公告)号：US20170179127A1

公开(公告)日：2017-06-22

申请号：US14974136

申请日：2015-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. Holt ,  Jody A. Fronheiser ,  Kangguo Cheng ,  Shogo Mochizuki ,  Stephen W. Bedell

IPC: H01L27/092 ,  H01L29/15 ,  H01L21/8238 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/155 ,  H01L29/66795

Abstract: An aspect of the disclosure includes a semiconductor structure comprising: a set of fins on a substrate, the set of fins including a relaxed silicon germanium layer; and a dielectric between each fin in the set of fins; wherein each fin in a n-type field effect transistor (nFET) region further includes a strained silicon layer over the relaxed silicon germanium layer of each fin in the nFET region; wherein each fin in a p-type field effect transistor (pFET) region further includes a strained silicon germanium layer over the relaxed silicon germanium layer of each fin in the pFET region.

公开(公告)号：US09601624B2

公开(公告)日：2017-03-21

申请号：US14585742

申请日：2014-12-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Dominic J. Schepis

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/161 ,  H01L29/06 ,  H01L21/84 ,  H01L21/02 ,  H01L29/167 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/7624 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66795 ,  H01L29/7848

Abstract: A method of fabricating a semiconductor device where: (i) the fins are formed over a porous semiconductor material layer (for example, a silicon layer); and (ii) the porous semiconductor layer is then oxidized to form an insulator layer (for example, a SiO2 buried oxide layer). The pores in the porous semiconductor layer facilitate reliable oxidation of the insulator layer by allowing penetration of gaseous oxygen (O2) throughout the layer as it is oxidized to form the insulator layer. In some of these embodiments, a thin non-porous semiconductor layer is located over the porous semiconductor layer (prior to its oxidation) to allow strained epitaxial growth of material to be used in making source regions and drain regions of the finished semiconductor device (for example, a FINFET).

公开(公告)号：US09478651B2

公开(公告)日：2016-10-25

申请号：US14732680

申请日：2015-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L29/06 ,  H01L29/778 ,  H01L27/088 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/095 ,  H01L29/872 ,  H01L29/205 ,  H01L29/66 ,  H01L21/683 ,  G06F17/50 ,  H01L29/20 ,  H01L29/40

CPC classification number: H01L29/7786 ,  G06F17/5045 ,  G06F17/5063 ,  H01L21/6835 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/088 ,  H01L27/095 ,  H01L29/0634 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/872 ,  H01L2221/68363

Abstract: A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both re-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions.

Abstract translation: 电路包括具有栅极的第一场效应晶体管，第一漏极 - 源极端子和第二漏极 - 源极端子; 以及具有栅极的第二场效应晶体管，第一漏极 - 源极端子和第二漏极 - 源极端子。 第二场效应晶体管和第一场效应晶体管是相同类型的，即重新沟道晶体管或两个p沟道晶体管。 第一场效应晶体管的第二漏极 - 源极端子耦合到第二场效应晶体管的第一漏极 - 源极端子; 并且第二场效应晶体管的栅极耦合到第二场效应晶体管的第一漏极 - 源极端子。 所得到的三端子器件可以替代否则在所提出的工作条件下会损坏的单个场效应晶体管。

公开(公告)号：US09406717B2

公开(公告)日：2016-08-02

申请号：US14725151

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/146

CPC classification number: H01L27/14692 ,  H01L27/1461 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14687

Abstract: A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.

公开(公告)号：US09331229B2

公开(公告)日：2016-05-03

申请号：US14147939

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L31/00 ,  H01L21/00 ,  H01L31/075 ,  H01L31/0304 ,  H01L31/074

CPC classification number: H01L31/075 ,  H01L31/03046 ,  H01L31/074 ,  Y02E10/544 ,  Y02P70/521

Abstract: An InxGa1-xAs interlayer is provided between a III-V base and an intrinsic amorphous semiconductor layer of a heterojunction III-V solar cell structure. Improved surface passivation and open circuit voltage may be obtained through the incorporation of the interlayer within the structure.

Abstract translation: 在III-V基极和异质结III-V族太阳能电池结构的本征非晶半导体层之间提供In x Ga 1-x As夹层。 可以通过在结构内并入中间层来获得改进的表面钝化和开路电压。

公开(公告)号：US09240432B2

公开(公告)日：2016-01-19

申请号：US14020473

申请日：2013-09-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L27/146

CPC classification number: H01L27/14692 ,  H01L27/1461 ,  H01L27/1462 ,  H01L27/14621 ,  H01L27/14625 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14645 ,  H01L27/14687

Abstract: A method for forming a back-illuminated image sensor includes forming a higher doped crystalline layer on a crystalline substrate, growing a lower doped crystalline layer on the higher doped crystalline layer and forming a photodiode and component circuitry from the lower doped crystalline layer. Metallization structures are formed to make connections to and between components. The crystalline substrate is removed to expose the higher doped crystalline layer. An optical component structure is provided on an exposed surface of the higher doped crystalline layer to receive light therein such that the higher doped crystalline layer provides a passivation layer for the photodiode and the component circuitry.