公开(公告)号：US20240213127A1

公开(公告)日：2024-06-27

申请号：US18522911

申请日：2023-11-29

Applicant: GAN SYSTEMS INC.

Inventor： Abhinandan DIXIT ,  An-Sheng CHENG ,  Di CHEN ,  Hossein MOUSAVIAN

IPC: H01L23/495 ,  H01L21/8234 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L21/823475 ,  H01L23/49568 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16056 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/1033 ,  H01L2924/13064

Abstract: A laminated embedded die package for a power semiconductor device, wherein a laminated body comprises a layup of a plurality of electrically conductive layers and dielectric layers. The die may be mounted in thermal contact with a leadframe. Electrical connections between contact areas of the die, external contact pads of the package and internal conductive layers are made by electrically conductive vias or microvias, formed by laser drilling of vias through the dielectric layers, which are then filled with conductive metal. A plurality of unfilled half-vias are arranged around edges of the laminated body adjacent external contact pads. Half-vias are formed by laser or mechanical drilling along scribe lines before singulation of packages. Surface plating of the half-vias comprises a solder wettable material. The half-vias are unfilled to form a wettable flank which allows for lateral wicking of solder during surface mounting, to facilitate optical inspection of solder reliability.

公开(公告)号：US20240213125A1

公开(公告)日：2024-06-27

申请号：US18085684

申请日：2022-12-21

Applicant: GaN Systems Inc.

Inventor： Abhinandan DIXIT

IPC: H01L23/495 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L23/49565 ,  H01L23/295 ,  H01L23/3107

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor switching devices is disclosed, wherein a power semiconductor die is mounted on a leadframe and embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. Electrical connections between contact pads of the power semiconductor die and external contact pads of the package comprise conductive vias extending through the dielectric layers. Edges of the leadframe are structured to provide vertical and lateral interlocking of the leadframe with surrounding dielectric, e.g. by providing a leadframe having a laterally scalloped and vertically undercut edge structure. Edges of the leadframe may be beveled.

公开(公告)号：US20230019052A1

公开(公告)日：2023-01-19

申请号：US17945231

申请日：2022-09-15

Applicant: GaN Systems Inc.

Inventor： Cameron MCKNIGHT-MACNEIL ,  Abhinandan DIXIT ,  Ahmad MIZAN ,  An-Sheng CHENG

IPC: H01L23/00 ,  B23K26/06 ,  B23K26/364 ,  B23K26/60

Abstract: Embedded die packaging for semiconductor devices and methods of fabrication wherein conductive vias are provided to interconnect contact areas on the die and package interconnect areas. Before embedding, a protective masking layer is provided selectively on regions of the electrical contact areas where vias are to be formed by laser drilling. The material of the protective masking layer is selected to protect against over-drilling and/or to control absorption properties of surface of the pad metal to reduce absorption of laser energy during laser drilling of micro-vias, thereby mitigating physical damage, overheating or other potential damage to the semiconductor device. The masking layer may be resistant to surface treatment of other regions of the electrical contact areas, e.g. to increase surface roughness to promote adhesion of package dielectric.

公开(公告)号：US20240421196A1

公开(公告)日：2024-12-19

申请号：US18209128

申请日：2023-06-13

Applicant: GaN Systems Inc.

Inventor： Abhinandan DIXIT ,  Jayasimha PRASAD ,  Thomas MACELWEE ,  Vineet UNNI

IPC: H01L29/40 ,  H01L23/31 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778

Abstract: A GaN semiconductor power transistor structure with a slanted gate field plate, and a method of fabrication are disclosed. The gate field plate comprises a gate metal field plate and slanted gate field plate structure formed using contact metal and/or interconnect metal. The slanted structure of the gate field plate is defined by etching of a dielectric layer having a graded composition, to form a slanted opening that is filled with conductive metal. The dielectric thickness under the gate field plate and the slant angle are configured to shape appropriately the electric field in the region between the gate and drain.

公开(公告)号：US20230402342A1

公开(公告)日：2023-12-14

申请号：US18094477

申请日：2023-01-09

Applicant: GaN Systems Inc.

Inventor： Di CHEN ,  Juncheng LU ,  Ahmad MIZAN ,  Ruoyu HOU ,  Abhinandan DIXIT

IPC: H01L23/367 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L23/3672 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66462

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor switching devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers, and wherein a first thermal pad on one side of the package and a second thermal pad on an opposite side of the package provides for dual-side cooling. Example embodiments of the dual-side cooled package may be based on a bottom-side cooled layup with a primary bottom-side thermal pad and a secondary top-side thermal pad, or a top-side cooled layup with primary top-side thermal pad and a secondary bottom side thermal pad, using layups with or without a leadframe. For example, the power semiconductor switching device comprises a GaN power transistor, such as a GaN HEMT rated for operation at ≥100V or ≥600V, for switching tens or hundreds of Amps.