公开(公告)号：US20240213127A1

公开(公告)日：2024-06-27

申请号：US18522911

申请日：2023-11-29

Applicant: GAN SYSTEMS INC.

Inventor： Abhinandan DIXIT ,  An-Sheng CHENG ,  Di CHEN ,  Hossein MOUSAVIAN

IPC: H01L23/495 ,  H01L21/8234 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49575 ,  H01L21/823475 ,  H01L23/49568 ,  H01L24/16 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16056 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2924/1033 ,  H01L2924/13064

Abstract: A laminated embedded die package for a power semiconductor device, wherein a laminated body comprises a layup of a plurality of electrically conductive layers and dielectric layers. The die may be mounted in thermal contact with a leadframe. Electrical connections between contact areas of the die, external contact pads of the package and internal conductive layers are made by electrically conductive vias or microvias, formed by laser drilling of vias through the dielectric layers, which are then filled with conductive metal. A plurality of unfilled half-vias are arranged around edges of the laminated body adjacent external contact pads. Half-vias are formed by laser or mechanical drilling along scribe lines before singulation of packages. Surface plating of the half-vias comprises a solder wettable material. The half-vias are unfilled to form a wettable flank which allows for lateral wicking of solder during surface mounting, to facilitate optical inspection of solder reliability.

公开(公告)号：US20240213110A1

公开(公告)日：2024-06-27

申请号：US18085660

申请日：2022-12-21

Applicant: GaN Systems Inc.

Inventor： An-Sheng CHENG ,  Stephen COATES

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/29 ,  H01L23/495 ,  H01L23/522 ,  H01L23/528 ,  H01L29/40 ,  H01L29/417

CPC classification number: H01L23/3192 ,  H01L21/4828 ,  H01L21/56 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/49513 ,  H01L23/49562 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/32 ,  H01L29/401 ,  H01L29/41775 ,  H01L2224/32225 ,  H01L2924/1033 ,  H01L2924/13064

Abstract: Embedded die packaging for semiconductor power switching devices, wherein the package comprises a laminated body comprising a layer stack of a plurality of dielectric layers and conductive metal layers. A thermal contact area on a back-side of the die is attached to a leadframe. A patterned layer of conductive metallization on a front-side of the die provides electrical contact areas of the power semiconductor device. Before embedding, a protective dielectric layer is provided on the front-side of the die, extending around edges of the die. The protective dielectric layer provides a protective region that acts a cushion to protect edges of the die from damage during lamination. The protective dielectric material may extend over the electrical contact areas to protect against etch damage and damage during laser drilling of vias, thereby mitigating physical damage, overheating or other potential damage to the active region of the semiconductor device.

公开(公告)号：US20230019052A1

公开(公告)日：2023-01-19

申请号：US17945231

申请日：2022-09-15

Applicant: GaN Systems Inc.

Inventor： Cameron MCKNIGHT-MACNEIL ,  Abhinandan DIXIT ,  Ahmad MIZAN ,  An-Sheng CHENG

IPC: H01L23/00 ,  B23K26/06 ,  B23K26/364 ,  B23K26/60

Abstract: Embedded die packaging for semiconductor devices and methods of fabrication wherein conductive vias are provided to interconnect contact areas on the die and package interconnect areas. Before embedding, a protective masking layer is provided selectively on regions of the electrical contact areas where vias are to be formed by laser drilling. The material of the protective masking layer is selected to protect against over-drilling and/or to control absorption properties of surface of the pad metal to reduce absorption of laser energy during laser drilling of micro-vias, thereby mitigating physical damage, overheating or other potential damage to the semiconductor device. The masking layer may be resistant to surface treatment of other regions of the electrical contact areas, e.g. to increase surface roughness to promote adhesion of package dielectric.