公开(公告)号：US06878580B2

公开(公告)日：2005-04-12

申请号：US10341563

申请日：2003-01-13

申请人： Geum-jong Bae ,  Nae-in Lee ,  Ki-chul Kim ,  Hwa-sung Rhee ,  Sang-su Kim ,  Jung-il Lee

发明人： Geum-jong Bae ,  Nae-in Lee ,  Ki-chul Kim ,  Hwa-sung Rhee ,  Sang-su Kim ,  Jung-il Lee

IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234

CPC分类号： H01L21/26586 ,  H01L21/2807 ,  H01L21/28114 ,  H01L29/42376

摘要： A semiconductor device having a gate with a negative slope and a method of manufacturing the same. A poly-SiGe layer with a Ge density profile which decreases linearly from the bottom of the gate toward the top of the gate is formed and a poly-SiGe gate having a negative slope is formed by patterning the poly-SiGe layer. It is possible to form a gate whose bottom is shorter than its top defined by photolithography by taking advantage of the variation of etching characteristics with Ge density when patterning. Accordingly, the gate is compact enough for a short channel device and gate resistance can be reduced.

摘要翻译： 一种具有负斜率栅极的半导体器件及其制造方法。 形成具有从栅极底部向栅极顶部线性减小的Ge密度分布的多晶硅层，并且通过对多晶硅层进行构图来形成具有负斜率的多晶硅栅极。 通过在图案化时利用Ge密度的蚀刻特性的变化，可以形成底部短于通过光刻限定的顶部的栅极。 因此，门对于短通道器件足够紧凑，并且可以减小栅极电阻。

公开(公告)号：US06815320B2

公开(公告)日：2004-11-09

申请号：US10444221

申请日：2003-05-23

申请人： Sang-su Kim ,  Geum-jong Bae ,  Ki-chul Kim ,  Jung-il Lee ,  Hwa-sung Rhee

发明人： Sang-su Kim ,  Geum-jong Bae ,  Ki-chul Kim ,  Jung-il Lee ,  Hwa-sung Rhee

IPC分类号： H01L213205

CPC分类号： H01L29/6653 ,  H01L21/823481 ,  H01L29/6656 ,  H01L29/6659

摘要： Provided is a method for fabricating a semiconductor device. According to the method, an insolating layer which defines an active region on a semiconductor substrate is formed and a gate is formed on the active region of the semiconductor substrate. A first spacer layer which covers the gate and is extended to cover the isolating layer is formed as a first insulating material. A second spacer layer is formed on the first spacer layer as a second insulating material. A second spacer which remains on the sidewalls of the gate by removing some portions of the second spacer layer is formed. A first spacer by a portion of the first spacer layer, which is protected by the second spacer by partially etching the exposed portions of the first spacer layer using the second spacer as a mask so as to reduce the thickness of the first spacer layer, and a protection layer, which protects the insulating layer by remaining the portion of the first spacer of which thickness is reduced, are formed. The second spacer is selectively removed and a gate spacer of the first spacer is formed by removing the remaining protection layer.

摘要翻译： 提供一种制造半导体器件的方法。 根据该方法，形成在半导体衬底上限定有源区的绝缘层，并且在半导体衬底的有源区上形成栅极。 覆盖栅极并延伸以覆盖隔离层的第一间隔层形成为第一绝缘材料。 第二间隔层作为第二绝缘材料形成在第一间隔层上。 形成通过去除第二间隔层的一些部分而保留在栅极的侧壁上的第二间隔物。 第一间隔物通过第一间隔层的一部分被第二间隔物保护，通过使用第二间隔物作为掩模部分蚀刻第一间隔层的暴露部分以减小第一间隔层的厚度，以及 形成保护层，其通过保留厚度减小的第一间隔物的部分来保护绝缘层。 选择性地去除第二间隔物，并且通过去除剩余的保护层来形成第一间隔物的栅极间隔物。

公开(公告)号：US06696328B2

公开(公告)日：2004-02-24

申请号：US10413387

申请日：2003-04-15

申请人： Hwa-sung Rhee ,  Geum-jong Bae ,  Sang-su Kim ,  Jung-il Lee ,  Young-ki Ha ,  Ki-chul Kim

发明人： Hwa-sung Rhee ,  Geum-jong Bae ,  Sang-su Kim ,  Jung-il Lee ,  Young-ki Ha ,  Ki-chul Kim

IPC分类号： H01L218238

CPC分类号： H01L21/823842 ,  Y10S438/933

摘要： A CMOS gate electrode formed using a selective growth method and a fabrication method thereof, wherein, in the CMOS gate electrode, a first gate pattern of polysilicon germanium (poly-SiGe) is formed on a PMOS region of a semiconductor substrate, and a second gate pattern of polysilicon is selectively grown from an underlying layer. Although the first gate pattern on the PMOS region is formed of poly-SiGe, the characteristics of the second gate pattern on the NMOS region do not deteriorate, thereby increasing the overall characteristics of a CMOS transistor.

摘要翻译： 一种使用选择性生长方法形成的CMOS栅电极及其制造方法，其中在CMOS栅电极中，在半导体衬底的PMOS区上形成多晶硅锗（poly-SiGe）的第一栅极图案， 从下层选择性地生长多晶硅的栅极图案。 尽管PMOS区上的第一栅极图案是由多晶硅形成的，但NMOS区域上的第二栅极图案的特性不会恶化，从而增加了CMOS晶体管的总体特性。

公开(公告)号：US20060157775A1

公开(公告)日：2006-07-20

申请号：US11378295

申请日：2006-03-20

申请人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

发明人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

公开(公告)号：US07566928B2

公开(公告)日：2009-07-28

申请号：US11269624

申请日：2005-11-09

申请人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

发明人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

摘要翻译： 字节操作的非易失性半导体存储器件能够一次一个字节地擦除存储的数据。 字节存储单元可以包括1字节存储晶体管的存储单元阵列。 1字节存储晶体管可以沿一个方向布置，每个包括结区域和形成在有源区域中的沟道区域。 字节存储单元可以包括字节选择晶体管。 选择晶体管可以设置在有源区域中并且包括与每个1字节存储晶体管的结直接相邻的结区域。 字节选择晶体管可以布置在垂直于1字节存储晶体管的排列方向的1字节存储晶体管的上方或下方。

公开(公告)号：US20060054965A1

公开(公告)日：2006-03-16

申请号：US11269624

申请日：2005-11-09

申请人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

发明人： Sung-ho Kim ,  Nae-in Lee ,  Kwang-wook Koh ,  Geum-jong Bae ,  Ki-chul Kim ,  Jin-hee Kim ,  In-wook Cho ,  Sang-su Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/792

摘要： Byte-operational nonvolatile semiconductor memory devices are capable of erasing stored data one byte at a time. A byte memory cell may include a memory cell array of 1-byte memory transistors. The 1-byte memory transistors may be arranged in one direction, each including a junction region and a channel region formed in an active region. A byte memory cell may include a byte select transistor. The select transistor may be disposed in the active region and including a junction region that is directly adjacent to a junction of each of the 1-byte memory transistors. The byte select transistor may be disposed over or under the 1-byte memory transistors perpendicular to the arranged direction of the 1-byte memory transistors.

公开(公告)号：US20060033152A1

公开(公告)日：2006-02-16

申请号：US11183614

申请日：2005-07-18

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

IPC分类号： H01L29/788

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A non-volatile memory device having improved electrical characteristics and a method of fabricating the non-volatile memory device are provided. The non-volatile memory device includes a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed, a trapping structure, which is interposed between the semiconductor substrate and the gate electrode and comprises an electron tunneling layer and a charge trapping layer, and an electron back-tunneling prevention layer, which is interposed between the gate electrode and the charge trapping layer, prevents electrons in the gate electrode from back-tunneling through the charge trapping layer, and is formed of a metal having a higher work function than the gate electrode.

公开(公告)号：US07586137B2

公开(公告)日：2009-09-08

申请号：US11200491

申请日：2005-08-09

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A non-volatile memory device having an asymmetric channel structure is provided. The non-volatile memory device includes a semiconductor substrate, a source region and a drain region which are formed in the semiconductor substrate and doped with n-type impurities, a trapping structure which includes a tunneling layer, which is disposed on a predetermined region of the semiconductor substrate and through which charge carriers are tunneled, and a charge trapping layer, which is formed on the tunneling layer and traps the tunneled charge carriers, a gate insulating layer which is formed on the trapping structure and the exposed semiconductor substrate, a gate electrode which is formed on the gate insulating layer, and a channel region which is formed between the source region and the drain region and includes a first channel region formed on a lower part of the trapping structure and a second channel region formed on a lower part of the gate insulating layer, the threshold voltage of the first channel region being lower than that of the second channel region.

摘要翻译： 提供了具有非对称沟道结构的非易失性存储器件。 非易失性存储器件包括形成在半导体衬底中并掺杂有n型杂质的半导体衬底，源极区和漏极区，包括隧穿层的俘获结构，其被布置在 半导体衬底和通过其电荷载流子被隧道化;以及电荷俘获层，其形成在隧穿层上并俘获隧穿电荷载流子;形成在俘获结构和暴露的半导体衬底上的栅极绝缘层，栅极 形成在栅极绝缘层上的电极和形成在源极区域和漏极区域之间的沟道区域，并且包括形成在捕获结构的下部的第一沟道区域和形成在栅极绝缘层的下部的第二沟道区域 所述第一沟道区的阈值电压低于所述第二沟道区的阈值电压。

公开(公告)号：US07473961B2

公开(公告)日：2009-01-06

申请号：US11183614

申请日：2005-07-18

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Jin-hee Kim ,  Sang-su Kim

IPC分类号： H01L29/792

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A non-volatile memory device having improved electrical characteristics and a method of fabricating the non-volatile memory device are provided. The non-volatile memory device includes a gate electrode, which is formed on a semiconductor substrate on which source and drain regions are formed, a trapping structure, which is interposed between the semiconductor substrate and the gate electrode and comprises an electron tunneling layer and a charge trapping layer, and an electron back-tunneling prevention layer, which is interposed between the gate electrode and the charge trapping layer, prevents electrons in the gate electrode from back-tunneling through the charge trapping layer, and is formed of a metal having a higher work function than the gate electrode.

摘要翻译： 提供了具有改善的电特性的非易失性存储器件以及制造该非易失性存储器件的方法。 非易失性存储器件包括形成在其上形成有源极和漏极区域的半导体衬底上的栅电极，该栅极电极介于半导体衬底和栅电极之间，并且包括电子隧穿层和 电荷捕获层和插入在栅电极和电荷捕获层之间的电子反向穿隧防止层防止栅电极中的电子通过电荷捕获层反向隧穿，并且由具有 工作功能比栅电极高。

公开(公告)号：US20060027854A1

公开(公告)日：2006-02-09

申请号：US11200491

申请日：2005-08-09

申请人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

发明人： Ki-chul Kim ,  Geum-jong Bae ,  In-wook Cho ,  Byoung-jin Lee ,  Sang-su Kim ,  Jin-hee Kim ,  Byou-ree Lim

IPC分类号： H01L29/76

CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/792

摘要： A non-volatile memory device having an asymmetric channel structure is provided. The non-volatile memory device includes a semiconductor substrate, a source region and a drain region which are formed in the semiconductor substrate and doped with n-type impurities, a trapping structure which includes a tunneling layer, which is disposed on a predetermined region of the semiconductor substrate and through which charge carriers are tunneled, and a charge trapping layer, which is formed on the tunneling layer and traps the tunneled charge carriers, a gate insulating layer which is formed on the trapping structure and the exposed semiconductor substrate, a gate electrode which is formed on the gate insulating layer, and a channel region which is formed between the source region and the drain region and includes a first channel region formed on a lower part of the trapping structure and a second channel region formed on a lower part of the gate insulating layer, the threshold voltage of the first channel region being lower than that of the second channel region.