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    Dual Inline Memory Module Socket
    1.
    发明申请
    Dual Inline Memory Module Socket 审中-公开
    双列直插式内存模块插座

    公开(公告)号：US20150004824A1

    公开(公告)日：2015-01-01

    申请号：US13931286

    申请日：2013-06-28

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： Vincent Nguyen ,  Binh Nguyen ,  Melvin K. Benedict ,  Minh H. Nguyen

    IPC: H01R13/629 ,  G01R31/04

    CPC classification number: G01R31/041 ,  H01R12/7029 ,  H01R13/641

    Abstract: The present disclosure describes, in one example, a dual inline memory module socket. The dual inline memory module socket includes a base to receive a memory module. The base further comprises a first detection pin and a second detection pin. A latch may be coupled to the base and is to electrically couple the first detection pin to the second detection pin in a dosed position to enable a determination that the memory module is properly seated.

    Abstract translation: 本公开在一个示例中描述了双列直插存储器模块插座。 双列直插式内存模块插座包括一个接收内存模块的基座。 基座还包括第一检测引脚和第二检测引脚。 闩锁可以联接到基座并且将电子耦合到处于计量位置的第一检测销到第二检测销，以使得可以确定存储器模块正确就位。

    Flow control for a Serial Peripheral Interface bus
    3.
    发明授权
    Flow control for a Serial Peripheral Interface bus 有权
    串行外设接口总线的流量控制

    公开(公告)号：US09003091B2

    公开(公告)日：2015-04-07

    申请号：US13655241

    申请日：2012-10-18

    Applicant: Hewlett-Packard Development Company, L.P.

    Inventor： David F. Heinrich ,  Theodore F. Emerson ,  Kevin B. Leigh ,  Vincent Nguyen ,  Andrew Brown ,  Gary Thome

    IPC: G06F13/00 ,  G06F3/00 ,  G06F13/42

    CPC classification number: G06F13/4291

    Abstract: Systems and methods for flow control within a Serial Peripheral Interface without additional signal lines are included herein. In one example, a method includes generating a flow control command. The method also includes sending the flow control command from a master device to a slave device with a Serial Peripheral Interface. In addition, the method includes sending a memory address from the master device to the slave device. Furthermore, the method includes detecting a ready indicator in the master device. The method also includes waiting to receive a ready indicator and communicating with the slave device in response to the ready indicator.

    Abstract translation: 串行外设接口中没有附加信号线的流量控制的系统和方法在此包括在内。 在一个示例中，一种方法包括生成流控制命令。 该方法还包括使用串行外设接口将流控制命令从主设备发送到从设备。 此外，该方法包括从主设备向从设备发送存储器地址。 此外，该方法包括检测主设备中的就绪指示符。 该方法还包括等待接收就绪指示符并响应于就绪指示符与从设备进行通信。

    RUNTIME BACKUP OF DATA IN A MEMORY MODULE
    4.
    发明申请
    RUNTIME BACKUP OF DATA IN A MEMORY MODULE 有权
    在记忆模块中运行数据备份

    公开(公告)号：US20150261672A1

    公开(公告)日：2015-09-17

    申请号：US14435167

    申请日：2013-01-30

    Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

    Inventor： Vincent Nguyen ,  Binh Nguyen ,  William C. Hallowell ,  Raghavan V. Venugopal

    IPC: G06F12/08 ,  G06F3/06

    CPC classification number: G06F12/0804 ,  G06F3/0619 ,  G06F3/0656 ,  G06F3/0685 ,  G06F2003/0691 ,  G06F2212/1032 ,  G06F2212/202 ,  G11C14/0018

    Abstract: During runtime of a system, a memory controller is caused to relinquish control of a memory module that includes a volatile memory and a non-volatile memory. After the triggering, an indication is activated to the memory module, the indication causing a backup operation in the memory module, the backup operation being controlled by an internal controller in the memory module, and the backup operation involving a transfer of data from the volatile memory to the non-volatile memory in the memory module.

    Abstract translation: 在系统的运行期间，使存储器控制器放弃对包含易失性存储器和非易失性存储器的存储器模块的控制。 触发后，指示被激活到存储器模块，指示引起存储器模块中的备份操作，备份操作由存储器模块中的内部控制器控制，并且备份操作涉及从易失性的数据传输 内存到内存模块中的非易失性存储器。

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