公开(公告)号：US20210143255A1

公开(公告)日：2021-05-13

申请号：US17080946

申请日：2020-10-27

Applicant: HITACHI, LTD.

Inventor： Takeru SUTO ,  Naoki TEGA ,  Naoki WATANABE ,  Hiroshi MIKI

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

Abstract: Provided is a semiconductor device whose performance is improved. A p type body region is formed in an n type semiconductor layer containing silicon carbide, and a gate electrode is formed on the body region with a gate insulating film interposed therebetween. An n type source region is formed in the body region on a side surface side of the gate electrode, and the body region and a source region are electrically connected to a source electrode. A p type field relaxation layer FRL is formed in the semiconductor layer on the side surface side of the gate electrode, and the source electrode is electrically connected to the field relaxation layer FRL. The field relaxation layer FRL constitutes a part of the JFET 2Q which is a rectifying element, and a depth of the field relaxation layer FRL is shallower than a depth of the body region.

公开(公告)号：US20190229211A1

公开(公告)日：2019-07-25

申请号：US16216333

申请日：2018-12-11

Applicant: HITACHI, LTD.

Inventor： Yuan BU ,  Hiroshi MIKI ,  Naoki TEGA ,  Naoki WATANABE ,  Digh HISAMOTO ,  Takeru SUTO

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/417 ,  H01L29/36 ,  H01L29/423 ,  H01L29/47 ,  H01L29/04 ,  H01L29/66 ,  H01L21/02 ,  H01L21/04 ,  H01L29/08 ,  H01L29/10

Abstract: A silicon carbide semiconductor device includes an n-type silicon carbide semiconductor substrate, a drain electrode electrically connected to a rear face, an n-type semiconductor layer having a second impurity concentration lower than the first impurity concentration, a p-type first semiconductor region, an n-type second semiconductor region, an n-type third semiconductor region, a trench having a first side face and a second side face opposing to each other and a third side face intersecting with the first side face and the second side face, a gate electrode formed in the trench with a gate insulating film interposed therebetween, a metal layer electrically connected to the third semiconductor region, and a source electrode electrically connecting the second semiconductor region and the metal layer to each other.

公开(公告)号：US20170330961A1

公开(公告)日：2017-11-16

申请号：US15524153

申请日：2015-01-19

Applicant: HITACHI, LTD.

Inventor： Naoki TEGA ,  Naoki WATANABE ,  Shintaroh SATO

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/8258

CPC classification number: H01L29/66893 ,  H01L21/8258 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7825

Abstract: An object of the present invention is to provide high-performance highly-reliable power semiconductor device.The semiconductor device according to the present invention is provided with a semiconductor substrate of a first conductive type, a drain electrode formed on a back side of the semiconductor substrate, a drift layer of the first conductive type formed on a semiconductor substrate, a source area of the first conductive type, a current-diffused layer of the first conductive type electrically connected to the drift layer, a body layer of a second conductive type reverse to the first conductive type in contact with the source area and the current-diffused layer, a trench which pierces the source area, the body layer and the current-diffused layer, which is shallower than the body layer, and the bottom of which is in contact with the body layer, a gate insulating film formed on an inner wall of the trench, a gate electrode formed on the gate insulating film, and a gate insulating film protective layer formed between the current-diffused layer and the gate electrode.

公开(公告)号：US20180026127A1

公开(公告)日：2018-01-25

申请号：US15625178

申请日：2017-06-16

Applicant: HITACHI, LTD.

Inventor： Takahiro MORIKAWA ,  Naoki WATANABE ,  Hiroyuki YOSHIMOTO

IPC: H01L29/78 ,  H01L21/04 ,  H01L29/16 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7802 ,  H01L21/0465 ,  H01L21/047 ,  H01L29/0657 ,  H01L29/0688 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1033 ,  H01L29/1041 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068 ,  H01L29/66712

Abstract: A semiconductor device has an active region in which a plurality of unit cells are regularly arranged, each of the unit cells including: a channel region having a first conductivity type and formed over a front surface of a semiconductor substrate; a source region having a second conductivity type different from the first conductivity type and formed over the front surface of the semiconductor substrate in such a manner as to be in contact with the channel region; and a JFET region having the second conductivity type and is formed over the front surface of the semiconductor substrate on the opposite side of the channel region from the source region in such a manner as to be in contact with the channel region. The channel region is comprised of a first channel region and a second channel region higher than the first channel region in impurity concentration, over the front surface of the semiconductor substrate.

公开(公告)号：US20230197782A1

公开(公告)日：2023-06-22

申请号：US17922428

申请日：2021-06-03

Applicant: HITACHI, LTD.

Inventor： Naoki WATANABE ,  Yuan BU

IPC: H01L29/08 ,  H01L29/66 ,  H01L21/268 ,  H01L29/16

CPC classification number: H01L29/0821 ,  H01L29/0804 ,  H01L29/66325 ,  H01L21/268 ,  H01L29/1608

Abstract: To realize a highly reliable IGBT that suppresses the bipolar degradation by preventing the occurrence of a defect on a boundary between a contact region and a silicide layer. As a means to realize the above, a semiconductor device includes: a collector region that is formed on a lower surface of a semiconductor substrate and forms an IGBT; and a collector electrode that is formed on a lower surface of the collector region via a silicide layer. The collector region and the silicide layer contains aluminum, first metal being more easily bondable to silicon than aluminum, and second metal being more easily bondable to carbon than aluminum.

公开(公告)号：US20210351271A1

公开(公告)日：2021-11-11

申请号：US16319140

申请日：2017-10-02

Applicant: HITACHI, LTD.

Inventor： Ryuusei FUJITA ,  Naoki WATANABE ,  Yuan BU

IPC: H01L29/16 ,  H01L25/07 ,  H01L29/739 ,  H01L29/861

Abstract: Dielectric breakdown resistance of a power module including a SiC-IGBT and a SiC diode is improved. The power module includes a SiC-IGBT 110 and a SiC diode 111, and a film thickness of a resin layer 323 covering an upper portion of an electric field relaxation region 320 of the SiC-IGBT 110 is larger than a chip thickness of the SiC-IGBT 110, that is, for example, 200 μm or more.

公开(公告)号：US20190081171A1

公开(公告)日：2019-03-14

申请号：US16046642

申请日：2018-07-26

Applicant: HITACHI, LTD.

Inventor： Naoki WATANABE

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/36 ,  H01L21/02 ,  H01L29/66 ,  H01L29/06 ,  H01L21/04 ,  H01L29/417 ,  H01L29/08 ,  H01L29/49 ,  H01L29/739

Abstract: A semiconductor device includes a semiconductor substrate having a main surface and a back surface, a drift region having a first conductivity type, a body region formed in the drift region and having a second conductivity type, a plurality of grooves passing through the body region from the main surface toward the back surface, a gate electrode formed in the plurality of grooves with a gate insulating film interposed therebetween, and an electric field relaxation layer provided below the plurality of grooves in the drift region and having a second conductivity type. The electric field relaxation layer continuously extends over the entire body region.

公开(公告)号：US20180331174A1

公开(公告)日：2018-11-15

申请号：US15533964

申请日：2015-02-12

Applicant: HITACHI, LTD.

Inventor： Naoki TEGA ,  Naoki WATANABE ,  Shintaroh SATO

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/04 ,  H02P27/08 ,  H02M7/5387 ,  B60L11/18

CPC classification number: H01L29/063 ,  B60L11/1812 ,  B60L2200/26 ,  B61C3/00 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/06 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/12 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/7813 ,  H02M7/53871 ,  H02P27/08

Abstract: An object of the present invention is to provide high-performance highly-reliable power semiconductor device.The semiconductor device according to the present invention is provided with a first conductive type semiconductor substrate, a drain electrode formed on a back side of the semiconductor substrate, a drift layer of the first conductive type formed on a surface side of the semiconductor substrate, a source area of the first conductive type, a current diffused layer of the first conductive type, a body layer of a second conductive type reverse to the first conductive type in contact with the source area and the current diffused layer, a trench which pierces the source area, the body layer and the current diffused layer, which is shallower than the body layer, and the bottom of which is in contact with the body layer, a high-concentration JFET layer of the first conductive type formed up to a deeper position than a boundary between the current diffused layer and the body layer, electrically connecting the drift layer and the current diffused layer, and having higher impurity concentration than the drift layer, a gate insulating film formed on an inner wall of the trench, and a gate electrode formed on the gate insulating film.

公开(公告)号：US20180151709A1

公开(公告)日：2018-05-31

申请号：US15577501

申请日：2015-06-01

Applicant: HITACHI, LTD.

Inventor： Hiroyuki YOSHIMOTO ,  Naoki WATANABE

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/417 ,  H01L29/36 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7395 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0273 ,  H01L21/0465 ,  H01L21/049 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/41708 ,  H01L29/4236 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7397 ,  H03K17/567

Abstract: An n-type drift layer DRL formed on a buffer layer BUF in a semiconductor device (SiC-IGBT) is configured so as to have (c1) an n-type first drift region DRL1 formed on the buffer layer BUF and (c2) an n-type second drift region DRL2 formed on the first drift region DRL1, (c3) an impurity concentration of the first drift region DRL1 is made lower than an impurity concentration of the buffer layer BUF and higher than an impurity concentration of the second drift region DRL2, and (c4) the first drift region DRL1 is made thinner than the second drift region DRL2. By forming the drift layer DRL so as to have a stacked structure as described above, an electric field on a surface on an emitter region side can be lowered at the OFF time of the semiconductor device even if a high voltage is applied. Moreover, at the time of switching, noises can be reduced since a carrier-stored region can be ensured.