公开(公告)号：US07173296B2

公开(公告)日：2007-02-06

申请号：US10959689

申请日：2004-10-06

申请人： Haowen Bu ,  Clinton L. Montgomery ,  Amitabh Jain

发明人： Haowen Bu ,  Clinton L. Montgomery ,  Amitabh Jain

IPC分类号： H01L29/76

CPC分类号： H01L29/4983 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/3145 ,  H01L21/31612 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.

摘要翻译： 本发明的一个实施例是制造半导体结构10的方法，其中通过无氢前体CVD工艺形成间隔氧化物层90。 本发明的另一实施例是具有氢含量小于1％的间隔氧化物层90的半导体结构10。

公开(公告)号：US07306995B2

公开(公告)日：2007-12-11

申请号：US10739973

申请日：2003-12-17

申请人： Haowen Bu ,  Clinton L. Montgomery ,  Amitabh Jain

发明人： Haowen Bu ,  Clinton L. Montgomery ,  Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L29/4983 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/02362 ,  H01L21/3145 ,  H01L21/31612 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An embodiment of the invention is a method of making a semiconductor structure 10 where the spacer oxide layer 90 is formed by a hydrogen free precursor CVD process. Another embodiment of the invention is a semiconductor structure 10 having a spacer oxide layer 90 with a hydrogen content of less than 1%.

公开(公告)号：US06831008B2

公开(公告)日：2004-12-14

申请号：US10261791

申请日：2002-09-30

申请人： Jiong-Ping Lu ,  Glenn J. Tessmer ,  Melissa M. Hewson ,  Donald S. Miles ,  Ralf B. Willecke ,  Andrew J. McKerrow ,  Brian K. Kirkpatrick ,  Clinton L. Montgomery

发明人： Jiong-Ping Lu ,  Glenn J. Tessmer ,  Melissa M. Hewson ,  Donald S. Miles ,  Ralf B. Willecke ,  Andrew J. McKerrow ,  Brian K. Kirkpatrick ,  Clinton L. Montgomery

IPC分类号： H01L2144

CPC分类号： H01L21/28052 ,  H01L21/28518 ,  H01L21/3185 ,  H01L21/321 ,  H01L21/3211 ,  H01L21/76834 ,  H01L29/665

摘要： A process for forming nickel silicide and silicon nitride structure in a semiconductor integrated circuit device is described. Good adhesion between the nickel silicide and the silicon nitride is accomplished by passivating the nickel suicide surface with nitrogen. The passivation may be performed by treating the nickel silicide surface with plasma activated nitrogen species. An alternative passivation method is to cover the nickel silicide with a film of metal nitride and heat the substrate to about 500° C. Another alternative method is to sputter deposit silicon nitride on top of nickel silicide.

摘要翻译： 描述了在半导体集成电路器件中形成硅化镍和氮化硅结构的工艺。 硅化镍和氮化硅之间的良好粘附性是通过用氮气钝化镍硅化物表面来实现的。 可以通过用等离子体活化的氮物种处理硅化镍表面来进行钝化。 替代的钝化方法是用金属氮化物膜覆盖硅化镍，并将衬底加热至约500℃。另一种替代方法是在硅化镍顶部溅射沉积氮化硅。

公开(公告)号：US07018925B2

公开(公告)日：2006-03-28

申请号：US10752885

申请日：2004-01-06

申请人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

发明人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

IPC分类号： H01L21/302

CPC分类号： H01L21/28202 ,  H01L21/02046 ,  H01L21/26506 ,  H01L21/28167 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3185 ,  H01L21/823462 ,  H01L29/518

摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

摘要翻译： 本发明提供一种制造双栅极半导体器件的方法。 在一个方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化 在暴露的氮化高压栅极电介质层上留下促进剂残留物，并将暴露的氮化高压电介质施加到高真空以除去促进剂残余物。

公开(公告)号：US07339240B2

公开(公告)日：2008-03-04

申请号：US11343680

申请日：2006-01-31

申请人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

发明人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

IPC分类号： H01L29/76

CPC分类号： H01L21/823462 ,  H01L21/28202 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518

摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

摘要翻译： 本发明提供一种制造双栅极半导体器件的方法。 一方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高电压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化叶片 在暴露的氮化高压栅极介电层上的促进剂残留物。 该方法还包括将暴露的氮化高压电介质经受等离子体去除促进剂残留物。

公开(公告)号：US07049242B2

公开(公告)日：2006-05-23

申请号：US10752886

申请日：2004-01-06

申请人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

发明人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

IPC分类号： H01L21/302

CPC分类号： H01L21/823462 ,  H01L21/28202 ,  H01L21/31111 ,  H01L21/31138 ,  H01L21/3144 ,  H01L21/82345 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/518

摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer. The method further includes subjecting the exposed nitridated, high voltage dielectric to a plasma to remove the accelerant residue.

摘要翻译： 本发明提供一种制造双栅极半导体器件的方法。 一方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高电压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化叶片 在暴露的氮化高压栅极介电层上的促进剂残留物。 该方法还包括将暴露的氮化高压电介质经受等离子体去除促进剂残留物。

公开(公告)号：US07402524B2

公开(公告)日：2008-07-22

申请号：US11292883

申请日：2005-12-02

申请人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

发明人： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

IPC分类号： H01L21/00

CPC分类号： H01L21/28202 ,  H01L21/02046 ,  H01L21/26506 ,  H01L21/28167 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3185 ,  H01L21/823462 ,  H01L29/518

摘要： The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

摘要翻译： 本发明提供一种制造双栅极半导体器件的方法。 在一个方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化 在暴露的氮化高压栅极电介质层上留下促进剂残留物，并将暴露的氮化高压电介质施加到高真空以除去促进剂残余物。