公开(公告)号：US09177806B2

公开(公告)日：2015-11-03

申请号：US13017828

申请日：2011-01-31

Applicant: Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01J37/00 ,  H01L21/00 ,  H01L21/28 ,  H01L21/316 ,  H01L21/318 ,  H01L29/51 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract translation: 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US07402524B2

公开(公告)日：2008-07-22

申请号：US11292883

申请日：2005-12-02

Applicant: Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

Inventor： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

IPC: H01L21/00

CPC classification number: H01L21/28202 ,  H01L21/02046 ,  H01L21/26506 ,  H01L21/28167 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3185 ,  H01L21/823462 ,  H01L29/518

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Abstract translation: 本发明提供一种制造双栅极半导体器件的方法。 在一个方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化 在暴露的氮化高压栅极电介质层上留下促进剂残留物，并将暴露的氮化高压电介质施加到高真空以除去促进剂残余物。

公开(公告)号：US20110120374A1

公开(公告)日：2011-05-26

申请号：US13017828

申请日：2011-01-31

Applicant: Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/469

CPC classification number: H01L21/28158 ,  C23C16/45557 ,  C23C16/4582 ,  H01J37/32752 ,  H01J37/32825 ,  H01J37/32899 ,  H01J2237/3321 ,  H01L21/02181 ,  H01L21/0223 ,  H01L21/02255 ,  H01L21/02318 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02329 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28035 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28229 ,  H01L21/3105 ,  H01L21/31604 ,  H01L21/318 ,  H01L21/3205 ,  H01L21/324 ,  H01L21/67161 ,  H01L21/67167 ,  H01L21/67196 ,  H01L21/67201 ,  H01L21/6776 ,  H01L29/42364 ,  H01L29/4908 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract translation: 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US06924239B2

公开(公告)日：2005-08-02

申请号：US10684897

申请日：2003-10-14

Applicant: Hiroaki Niimi ,  Husam N. Alshareef ,  Ajith Varghese

Inventor： Hiroaki Niimi ,  Husam N. Alshareef ,  Ajith Varghese

IPC: H01L21/20 ,  H01L21/28 ,  H01L21/302 ,  H01L21/306 ,  H01L21/31 ,  H01L21/314 ,  H01L21/316 ,  H01L21/36

CPC classification number: H01L21/28202 ,  H01L21/02046 ,  H01L21/28185 ,  H01L21/3144 ,  H01L21/31662

Abstract: The present invention is generally directed towards a method for removing hydrocarbon contamination from a substrate prior to a nitridation step, therein providing for a generally uniform nitridation of the substrate. The method comprises placing the substrate in a process chamber and flowing an oxygen-source gas into the process chamber. A first plasma is formed in the process chamber for a first predetermined amount of time, wherein the hydrocarbons combine with one or more species of the oxygen-source gas in radical form to form product gases. The gases are removed from the process chamber and a nitrogen-source gas is flowed into the process chamber. A second plasma is then formed in the process chamber for a second predetermined amount of time, therein nitriding the substrate in a significantly uniform manner.

Abstract translation: 本发明一般涉及一种在氮化步骤之前从基底去除烃类污染物的方法，其中提供基底的大致均匀的氮化。 该方法包括将基板放置在处理室中并将氧源气体流入处理室。 第一等离子体在处理室中形成第一预定量的时间，其中烃与一种或多种以自由基形式的氧源气体组合以形成产物气体。 气体从处理室中移出，氮源气体流入处理室。 然后在处理室中形成第二等离子体第二预定量的时间，其中以显着均匀的方式氮化基板。

公开(公告)号：US06730566B2

公开(公告)日：2004-05-04

申请号：US10264729

申请日：2002-10-04

Applicant: Hiroaki Niimi ,  Rajesh Khamankar ,  Husam N. Alshareef

Inventor： Hiroaki Niimi ,  Rajesh Khamankar ,  Husam N. Alshareef

IPC: H01L218234

CPC classification number: H01L21/823462 ,  Y10S438/92

Abstract: A method is provided for non-thermally nitrided gate formation of high voltage transistor devices. The non-thermally nitrided gate formation is useful in the formation of dual thickness gate dielectric structures. The non-thermally nitrided gate formation comprises nitridation to introduce nitrogen atoms into the gate dielectric layer of the high voltage transistor devices to mitigate leakage associated with the high voltage transistor devices. The nitridation of the gate dielectric layer damages the surface of the gate dielectric layer. The damaged surface of the gate dielectric layer is removed by a relatively low temperature re-oxidation process. The low temperature re-oxidation process minimizes nitrogen loss during a subsequent photoresist stripping process and mitigates film densification, such that the structure can be readily etched by standard etching chemicals in subsequent processing.

Abstract translation: 提供了用于高压晶体管器件的非热氮化栅极形成的方法。 非热氮化栅极形成可用于双厚度栅极电介质结构的形成。 非热氮化栅极形成包括氮化以将氮原子引入到高压晶体管器件的栅极介电层中，以减轻与高压晶体管器件相关的泄漏。 栅极电介质层的氮化破坏了栅极电介质层的表面。 通过相对较低温度的再氧化工艺去除栅介电层的受损表面。 低温再氧化工艺在随后的光致抗蚀剂剥离过程中使氮损失最小化并减轻膜致密化，使得结构可以在随后的处理中通过标准蚀刻化学品容易地蚀刻。

公开(公告)号：US07226826B2

公开(公告)日：2007-06-05

申请号：US10826516

申请日：2004-04-16

Applicant: Husam N. Alshareef ,  Mark R. Visokay ,  Antonio Luis Pacheco Rotondaro ,  Luigi Colombo

Inventor： Husam N. Alshareef ,  Mark R. Visokay ,  Antonio Luis Pacheco Rotondaro ,  Luigi Colombo

IPC: H01L21/8238

CPC classification number: H01L21/321 ,  H01L21/28079 ,  H01L21/823835 ,  H01L21/823842

Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a first transistor (120) located over a semiconductor substrate (110), wherein the first transistor (120) has a metal gate electrode (135) having a work function, and a second transistor (160) located over the semiconductor substrate (110) and proximate the first transistor (120), wherein the second transistor (160) has a plasma altered metal gate electrode (175) having a different work function.

Abstract translation: 本发明提供一种半导体器件及其制造方法以及集成电路的制造方法。 半导体器件（100）以及其他可能的元件包括位于半导体衬底（110）上方的第一晶体管（120），其中第一晶体管（120）具有具有功函数的金属栅电极（135） 第二晶体管（160）位于半导体衬底（110）上并且靠近第一晶体管（120），其中第二晶体管（160）具有具有不同功函数的等离子体改变的金属栅电极（175）。

公开(公告)号：US07018925B2

公开(公告)日：2006-03-28

申请号：US10752885

申请日：2004-01-06

Applicant: Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

Inventor： Brian K. Kirkpatrick ,  Rajesh Khamankar ,  Malcolm J. Bevan ,  April Gurba ,  Husam N. Alshareef ,  Clinton L. Montgomery ,  Mark H. Somervell

IPC: H01L21/302

CPC classification number: H01L21/28202 ,  H01L21/02046 ,  H01L21/26506 ,  H01L21/28167 ,  H01L21/31105 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3185 ,  H01L21/823462 ,  H01L29/518

Abstract: The present invention provides a method for fabricating a dual gate semiconductor device. In one aspect, the method comprises forming a nitridated, high voltage gate dielectric layer over a semiconductor substrate, patterning a photoresist over the nitridated, high voltage gate dielectric layer to expose the nitridated, high voltage dielectric within a low voltage region, wherein the patterning leaves an accelerant residue on the exposed nitridated, high voltage gate dielectric layer, and subjecting the exposed nitridated, high voltage dielectric to a high vacuum to remove the accelerant residue.

Abstract translation: 本发明提供一种制造双栅极半导体器件的方法。 在一个方面，该方法包括在半导体衬底上形成氮化的高电压栅极电介质层，在氮化的高压栅极电介质层上形成光致抗蚀剂，以在低电压区域内露出氮化的高电压电介质，其中图案化 在暴露的氮化高压栅极电介质层上留下促进剂残留物，并将暴露的氮化高压电介质施加到高真空以除去促进剂残余物。

公开(公告)号：US06921703B2

公开(公告)日：2005-07-26

申请号：US10436848

申请日：2003-05-13

Applicant: Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

Inventor： Malcolm J. Bevan ,  Haowen Bu ,  Hiroaki Niimi ,  Husam N. Alshareef

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28202 ,  H01L29/4908 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

Abstract: Oxide growth of a gate dielectric layer that occurs between processes used in the fabrication of a gate dielectric structure can be reduced. The reduction in oxide growth can be achieved by maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth of the gate dielectric layer between at least two sequential process steps used in the fabrication the gate dielectric structure. Maintaining the gate dielectric layer in an ambient effective to mitigate oxide growth also improves the uniformity of nitrogen implanted in the gate dielectric.

Abstract translation: 可以减少在制造栅极电介质结构中使用的工艺之间发生的栅极介电层的氧化物生长。 氧化物生长的减少可以通过将栅极电介质层保持在有效的方式来实现，以在制造栅极电介质结构中的至少两个顺序的工艺步骤之间减轻栅极电介质层的氧化物生长。 维持栅极电介质层在有效减少氧化物生长的环境中也改善了注入栅电介质的氮的均匀性。

公开(公告)号：US07345001B2

公开(公告)日：2008-03-18

申请号：US10875482

申请日：2004-06-24

Applicant: Hiroaki Niimi ,  Husam N. Alshareef ,  Rajesh Khamankar ,  Toan Tran

Inventor： Hiroaki Niimi ,  Husam N. Alshareef ,  Rajesh Khamankar ,  Toan Tran

IPC: H01L29/72

CPC classification number: H01L21/3115 ,  H01L21/0214 ,  H01L21/02329 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/512 ,  H01L29/518 ,  H01L29/6656

Abstract: The present invention provides a gate dielectric having a flat nitrogen profile, a method of manufacture therefor, and a method of manufacturing an integrated circuit including the flat nitrogen profile. In one embodiment, the method of manufacturing the gate dielectric includes forming a gate dielectric layer (410) on a substrate (310), and subjecting the gate dielectric layer (410) to a nitrogen containing plasma process (510), wherein the nitrogen containing plasma process (510) has a ratio of helium to nitrogen of 3:1 or greater.

Abstract translation: 本发明提供一种具有平坦氮分布的栅极电介质及其制造方法，以及制造包含平坦氮分布的集成电路的方法。 在一个实施例中，制造栅极电介质的方法包括在衬底（310）上形成栅极电介质层（410），并对栅极电介质层（410）施加含氮等离子体工艺（510），其中含氮 等离子体工艺（510）的氦与氮的比例为3:1或更高。

公开(公告)号：US20170249983A1

公开(公告)日：2017-08-31

申请号：US15324319

申请日：2015-06-03

Applicant: Ji Hoon Park ,  Husam N. Alshareef ,  Mohd A. Khan ,  Ihab N. Odeh ,  SABIC Global Technologies B.V.

Inventor： Ji Hoon Park ,  Husam N. Alshareef ,  Mohd A. Khan ,  Ihab N. Odeh

IPC: G11C11/22 ,  H01L27/11509 ,  G11C11/56

CPC classification number: G11C11/2275 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2277 ,  G11C11/5657 ,  H01L27/11509 ,  H01L27/20

Abstract: Ferroelectric components, such as the ferroelectric field effect transistors (FeFETs), ferroelectric capacitors and ferroelectric diodes described above may be operated as multi-level memory cells as described by the present invention. Storing multiple bits of information in each multi-level memory cell may be performed by a controller coupled to an array of the ferroelectric components configured as ferroelectric memory cells. The controller may execute the steps of receiving a bit pattern for writing to a multi-level memory cell comprising a ferroelectric layer; selecting a pulse duration for applying a write pulse to the memory cell based, at least in part, on the received bit pattern; and applying at least one write pulse to the memory cell having the selected pulse duration, in which the at least one write pulse creates a remnant polarization within the ferroelectric layer that is representative of the received bit pattern.