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公开(公告)号：US20250081347A1
公开(公告)日：2025-03-06
申请号：US18820278
申请日：2024-08-30
Applicant: Industrial Technology Research Institute
Inventor： Chung-Wei Wang , Chen-Tsai Yang , Shu-Wei Kuo , Min-Hsiung Liang , Bor-Chuan Chuang
Abstract: An electrical connection device includes a mother board and a daughter board. The mother board includes a first board body with at least one cavity and a first electrical contact printed on the first board body. The daughter board includes a second board body and a second electrical contact printed on the second board body. At least one of the daughter board and the mother board includes at least one contour feature integrally formed with at least one of the first board body and the second board body. When the second board body is inserted into the at least one cavity of the first board body, the second electrical contact is electrically connected to the first electrical contact, and the daughter board is positioned in the mother board through the at least one contour feature.
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公开(公告)号：US11646259B2
公开(公告)日：2023-05-09
申请号：US17159012
申请日：2021-01-26
Applicant: Industrial Technology Research Institute
Inventor： Shu-Wei Kuo , Chen-Tsai Yang , Wei-Yuan Cheng , Chien-Hsun Chu , Shau-Fei Cheng
IPC: H01L23/498 , H01L23/00 , H01L23/31 , H01L21/48
CPC classification number: H01L23/49838 , H01L21/4857 , H01L23/3121 , H01L23/3135 , H01L23/49822 , H01L24/16 , H01L2224/16227 , H01L2924/18161
Abstract: Provided is a forming method of a redistribution structure including: forming a first redistribution layer and a first compensation circuit layer on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer, and the first compensation circuit layer and the first redistribution layer are electrically insulated from each other; forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; and forming a second redistribution layer and a second compensation circuit layer on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer and the second redistribution layer are electrically insulated from each other, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer.
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公开(公告)号：US10573587B2
公开(公告)日：2020-02-25
申请号：US15673422
申请日：2017-08-10
Applicant: Industrial Technology Research Institute
Inventor： Shu-Wei Kuo , Chun-Yi Cheng , Wei-Yuan Cheng
IPC: H01L23/498 , H01L21/48 , H01L21/683 , H01L21/768 , H01L21/56 , H01L23/31 , H01L23/00
Abstract: A package structure includes a redistribution layer, a chip, an encapsulant, an under bump supporting layer, an attachment layer and solder balls. The redistribution layer includes a first surface, a second surface opposite to the first surface and a patterned circuit layer disposed on the first surface, wherein an outer surface of the patterned circuit layer and the first surface are coplanar. The chip is disposed on the second surface and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface to encapsulate the chip. The under bump supporting layer is disposed on the first surface and includes openings for exposing the outer surface. The attachment layer covers the inner surface of each opening and the exposed portion of the patterned circuit layer. The solder balls are disposed in the openings respectively and electrically connected to the patterned circuit layer.
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公开(公告)号：US10249567B2
公开(公告)日：2019-04-02
申请号：US15853853
申请日：2017-12-25
Inventor： Jie-Mo Lin , Shu-Wei Kuo , Wei-Yuan Cheng , Chen-Tsai Yang
IPC: H01L23/528 , H01L21/48 , H01L23/00 , H01L23/498
Abstract: A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a first surface of the dielectric layer, at least one lower conductive wire disposed on a second surface of the dielectric layer, and vias penetrating the dielectric layer and connecting the at least one upper conductive wire and the at least one lower conductive wire. Each via has a cross-section at one upper conductive wire. The cross-section has a third width. The ratio of the third width to the thickness of the dielectric layer is less than or equal to 1. The ratio of the pitch between every two adjacent vias to the third width is greater than or equal to 0.5.
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公开(公告)号：US20200244094A1
公开(公告)日：2020-07-30
申请号：US16747541
申请日：2020-01-21
Applicant: Industrial Technology Research Institute
Inventor： Shu-Wei Kuo , Chang-Chung Yang
Abstract: A charging-and-discharging device and a charging-and-discharging method are provided. The charging-and-discharging device includes a renewable energy converter, an aluminum battery, a controller and a current converter. The renewable energy converter receives a power from a renewable energy power generation system. The controller is coupled to the renewable energy converter and the aluminum battery, wherein the controller configures a charging-and-discharging power of the aluminum battery, according to a power value of the power, to compensate the power so as to generate a compensated power. The current converter is coupled to the controller, wherein the current converter outputs the compensated power to a power grid after performing DC/AC converting.
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Patent Agency Ranking
公开(公告)号：US10366965B2
公开(公告)日：2019-07-30
申请号：US15856065
申请日：2017-12-28
Inventor： Shu-Wei Kuo , Wei-Yuan Cheng , Shau-Fei Cheng
IPC: H01L23/495 , H01L23/00 , H01L23/498 , H01L23/544 , H01L21/67 , H01L21/48 , H01L23/31
Abstract: A chip bonding apparatus for bonding a chip and a redistribution structure with each other is provided. The chip bonding apparatus includes a pick and place module and an alignment module. The pick and place module is suitable for picking up and placing the chip. The alignment module is movably connected to the pick and place module. The alignment module includes at least one alignment protrusion, wherein the at least one alignment protrusion extends toward at least one alignment socket included in the redistribution structure. Furthermore, a chip bonding method and a chip package structure are provided.
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公开(公告)号：US20190088600A1
公开(公告)日：2019-03-21
申请号：US15849593
申请日：2017-12-20
Inventor： Shu-Wei Kuo , Wei-Yuan Cheng , Chen-Tsai Yang , Jie-Mo Lin
Abstract: A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.
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公开(公告)号：US20140133009A1
公开(公告)日：2014-05-15
申请号：US13803168
申请日：2013-03-14
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor： Yi-Chun Liu , Shu-Wei Kuo , Ping-Chen Chen
CPC classification number: G03F7/20 , G02B26/005 , G02B2207/115 , G03F7/0035
Abstract: A method for manufacturing an electrowetting display unit includes the following steps. A first substrate and a second substrate are provided. A first conductive layer is disposed on one side of the first substrate. A second conductive layer is disposed on one side of the second substrate. A polymer layer, which includes a siloxane containing a light-induced cross linkable group and a Si—H bond, is disposed on the first conductive layer. The molecular weight of the monomer of the siloxane is equal to or greater than 5000. A part of the polymer layer is exposed to a light so as to form a plurality of hydrophobic sections. A hydrophilic section is developed by treating a developing agent. The hydrophilic section and the plurality of hydrophobic sections form a pattern layer together. Polar liquid and non-polar liquid are disposed between the pattern layer and the second conductive layer.
Abstract translation: 电润湿显示单元的制造方法包括以下步骤。 提供第一基板和第二基板。 第一导电层设置在第一基板的一侧。 第二导电层设置在第二基板的一侧。 包含含有光诱导的可交联基团和Si-H键的硅氧烷的聚合物层设置在第一导电层上。 硅氧烷的单体的分子量等于或大于5000.聚合物层的一部分暴露于光以形成多个疏水部分。 通过处理显影剂来开发亲水部分。 亲水部分和多个疏水部分一起形成图案层。 极性液体和非极性液体设置在图案层和第二导电层之间。
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公开(公告)号：US10461035B2
公开(公告)日：2019-10-29
申请号：US15849593
申请日：2017-12-20
Inventor： Shu-Wei Kuo , Wei-Yuan Cheng , Chen-Tsai Yang , Jie-Mo Lin
IPC: H01L23/538 , H01L23/14 , H01L23/15 , H01L23/31 , H01L23/00 , H01L21/48 , H01L21/56 , H01L23/498
Abstract: A semiconductor package structure includes a redistribution structure, a chip, an upper dielectric layer, a plurality of conductive members and an encapsulation layer. The redistribution structure includes a redistribution layer and a first dielectric layer disposed on the redistribution layer. The upper dielectric layer is disposed between the chip and the first dielectric layer of the redistribution structure, wherein the upper dielectric layer and the first dielectric layer are organic materials. A plurality of conductive members is disposed between the redistribution layer and the chip. Each conductive member has a first end adjacent to the chip and a second end adjacent to the redistribution structure, wherein the first end of said each conductive member contacts with the upper dielectric layer and the second end of said each conductive member contacts with the first dielectric layer.
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公开(公告)号：US09743513B2
公开(公告)日：2017-08-22
申请号：US14583235
申请日：2014-12-26
Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
Inventor： Shu-Wei Kuo , Kuo-Lung Lo , Cheng-Che Wu , Chen-Chu Tsai
CPC classification number: H05K1/0281 , H05K1/189 , H05K3/007 , H05K3/284 , H05K2201/10106 , H05K2201/10166 , H05K2201/2009 , H05K2203/1316
Abstract: According to embodiments of the disclosure, a flexible electronic device is provided. The flexible electronic device includes a flexible substrate, at least one component and at least one stress buffer. The component may be disposed on the flexible substrate and having a lateral surface. The stress buffer may be disposed adjacent to the lateral surface of the component and has a stiffness which is getting larger toward the component.
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