公开(公告)号：US11847011B2

公开(公告)日：2023-12-19

申请号：US17181832

申请日：2021-02-22

Applicant: Intel Corporation

Inventor： Praveen Mosalikanti ,  Nasser A. Kurd ,  Alexander Gendler

IPC: G06F1/3296 ,  H03L7/093 ,  G01R19/25 ,  H03L7/095 ,  H03K5/24 ,  H03K19/20

CPC classification number: G06F1/3296 ,  G01R19/2513 ,  H03K5/24 ,  H03K19/20 ,  H03L7/093 ,  H03L7/095

Abstract: An apparatus and method are described, which prior to an event that could result in frequency overshoot, sends a signal to a voltage regulator or generator requesting a temporary supply voltage and/or current boost. This enables a clocking source, such as a phase locked loop (PLL) to lock fast while not needing any long-term voltage guard bands. The apparatus and scheme allows for on-the-fly change in supply voltage and/or clock frequency for a processor with little to no impact on Vmin. During the clock frequency overshoot, the supply voltage is temporarily boosted and then reduced down to the expected voltage level of the power supply. Such boost allows for absorbing the clock frequency overshoot impact. The supply voltage level can be reduced in a step-wise fashion to avoid any potential undershoot in clock frequency.

公开(公告)号：US11385704B2

公开(公告)日：2022-07-12

申请号：US17183518

申请日：2021-02-24

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Igor Yanover ,  Gavri Berger ,  Edo Hachamo ,  Elkana Korem ,  Hanan Shomroni ,  Daniela Kaufman ,  Lev Makovsky ,  Haim Granot

IPC: G06F1/32 ,  G06F1/324 ,  G06F1/3206

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

公开(公告)号：US11042213B2

公开(公告)日：2021-06-22

申请号：US16370950

申请日：2019-03-30

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Yoni Aizik ,  Chen Ranel ,  Ido Melamed ,  Edward Vaiberman

IPC: G06F1/32 ,  G06F1/3296

Abstract: Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.

公开(公告)号：US10921872B2

公开(公告)日：2021-02-16

申请号：US16369136

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Elkana Korem ,  Hanan Shomroni ,  Nadav Shulman

IPC: G06F1/324 ,  G06F1/3287 ,  G06F1/3234 ,  G06F1/3293 ,  G06F1/329

Abstract: In an embodiment, a processor includes processing engines to execute instructions and power limit logic. The power limit logic is to: in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine; determine a ratio of the soft throttling events to the hard throttling events; compare the determined ratio to a desired goal; and adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal. Other embodiments are described and claimed.

公开(公告)号：US20200349312A1

公开(公告)日：2020-11-05

申请号：US16854788

申请日：2020-04-21

Applicant: Intel Corporation

Inventor： Tsvika Kurts ,  Alexander Gendler ,  Larisa Novakovsky ,  Anwar Azaarura Zaa'Rura ,  Afik Sela ,  Genadi Kazakevich ,  Alexandra Shainshein ,  Ariel Sabba

IPC: G06F30/3323 ,  G01R31/317 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36

Abstract: An apparatus, including: a deterministic monitored device; an interconnect to communicatively couple the monitored device to a support circuit; a super queue to queue transactions between the monitored device and the support circuit, the super queue including an operational segment and a shadow segment; a debug data structure; and a system management agent to monitor transactions in the operational segment, log corresponding transaction identifiers in the shadow segment, and write debug data to the debug data structure, wherein the debug data are at least partly based on the corresponding transaction identifiers.

公开(公告)号：US20200310511A1

公开(公告)日：2020-10-01

申请号：US16369793

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Igor Yanover ,  Gavri Berger ,  Edo Hachamo ,  Elkana Korem ,  Hanan Shomroni ,  Daniela Kaufman ,  Lev Makovsky ,  Haim Granot

IPC: G06F1/324 ,  G06F1/3206

Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.

公开(公告)号：US20200310509A1

公开(公告)日：2020-10-01

申请号：US16369136

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Elkana Korem ,  Hanan Shomroni ,  Nadav Shulman

IPC: G06F1/324 ,  G06F1/3234 ,  G06F1/3287 ,  G06F1/329 ,  G06F1/3293

Abstract: In an embodiment, a processor includes processing engines to execute instructions and power limit logic. The power limit logic is to: in response to a plurality of power spikes, perform a number of soft throttling events and a number of hard throttling events in a first processing engine; determine a ratio of the soft throttling events to the hard throttling events; compare the determined ratio to a desired goal; and adjust one or more throttling parameters in response to a determination that the determined ratio does not match the desired goal. Other embodiments are described and claimed.

公开(公告)号：US20200096569A1

公开(公告)日：2020-03-26

申请号：US16142591

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Michael Mishaeli ,  Larisa Novakovsky ,  Edward Brazil ,  Alexander Gendler

IPC: G01R31/3185 ,  G06F1/32 ,  G01R31/319

Abstract: In one embodiment, a processor includes a scan system controller to control test operations on the processor in response to test commands from an external test entity, and at least one core to execute instructions. The processor may further include a field scan controller to control a field test mode of the processor to perform a self-test of the at least one core during field operation, where the field scan controller is to obtain a test pattern from an external memory and cause the scan system controller to test circuitry of the first subsystem using the test pattern. Other embodiments are described and claimed.

公开(公告)号：US20190101969A1

公开(公告)日：2019-04-04

申请号：US15720801

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Krishnakanth V. Sistla ,  Ankush Varma ,  Ariel Szapiro

IPC: G06F1/30 ,  G06F1/32 ,  G06F12/084 ,  G06F12/0875

Abstract: In an embodiment, a processor includes a power control unit, a master processing engine, a set of slave processing engines, and a voltage regulator. The master processing engine is to, in response to a receipt of a change message from the power control unit, control the voltage regulator to adjust a voltage level provided to the master processing engine and the set of slave processing engines. Other embodiments are described and claimed.

公开(公告)号：US20180373315A1

公开(公告)日：2018-12-27

申请号：US15629872

申请日：2017-06-22

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Arkady Bramnik ,  Lev Makovsky

IPC: G06F1/32 ,  G06F11/10

CPC classification number: G06F1/3287 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F11/1004 ,  G06F11/1076

Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.