公开(公告)号：US20220012189A1

公开(公告)日：2022-01-13

申请号：US17485360

申请日：2021-09-25

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Robert G. Blankenship ,  Suresh S. Chittor ,  Kenneth C. Creta ,  Balint Fleischer ,  Michelle C. Jen ,  Mohan J. Kumar ,  Brian S. Morris

IPC: G06F13/16 ,  G06F13/38 ,  G06F12/14 ,  G06F13/42

Abstract: A shared memory controller is to service load and store operations received, over data links, from a plurality of independent nodes to provide access to a shared memory resource. Each of the plurality of independent nodes is to be permitted to access a respective portion of the shared memory resource. Interconnect protocol data and memory access protocol data are sent on the data links and transitions between the interconnect protocol data and memory access protocol data can be defined and identified.

公开(公告)号：US10671740B2

公开(公告)日：2020-06-02

申请号：US15946401

申请日：2018-04-05

Applicant: Intel Corporation

Inventor： Binata Bhattacharyya ,  Raghunandan Makaram ,  Amy L. Santoni ,  George Z. Chrysos ,  Simon P. Johnson ,  Brian S. Morris ,  Francis X. McKeen

IPC: G06F21/62 ,  G06F21/64 ,  G06F21/78 ,  G06F21/74 ,  G06F12/14 ,  G06F21/60

Abstract: A processor implementing techniques for supporting configurable security levels for memory address ranges is disclosed. In one embodiment, the processor includes a processing core a memory controller, operatively coupled to the processing core, to access data in an off-chip memory and a memory encryption engine (MEE) operatively coupled to the memory controller. The MEE is to responsive to detecting a memory access operation with respect to a memory location identified by a memory address within a memory address range associated with the off-chip memory, identify a security level indicator associated with the memory location based on a value stored on a security range register. The MEE is further to access at least a portion of a data item associated with the memory address range of the off-chip memory in view of the security level indicator.

公开(公告)号：US10360096B2

公开(公告)日：2019-07-23

申请号：US15462185

申请日：2017-03-17

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Eric L. Hendrickson

IPC: G06F11/00 ,  G06F11/08 ,  G06F11/16 ,  G06F13/00 ,  H04L1/00 ,  H04L1/18

Abstract: Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

公开(公告)号：US10198379B2

公开(公告)日：2019-02-05

申请号：US15669197

申请日：2017-08-04

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Jeffrey C. Swanson

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42

Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

公开(公告)号：US20160179718A1

公开(公告)日：2016-06-23

申请号：US14578407

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Jeffrey C. Swanson

IPC: G06F13/28 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/1642 ,  G06F13/382 ,  G06F13/4221

Abstract: A sequence of read returns are to be sent to a host device over a transactional buffered memory interface, where the sequence includes at least a first read return to a first read request and a second read return to a second read request. A tracker identifier of the second read return is encoded in the first read return and the first read return is sent with the tracker identifier of the second read return to the host device. The second read return is sent to the host device after the first read return is sent.

Abstract translation: 读取返回序列将通过事务缓冲存储器接口发送到主机设备，其中序列至少包括对第一读取请求的第一读取返回和第二读取返回到第二读取请求。 在第一读取返回中编码第二读取返回的跟踪器标识符，并且将第一读取返回与第二读取返回的跟踪器标识符一起发送到主机设备。 在发送第一次读取返回后，第二个读取返回被发送到主机设备。

公开(公告)号：US09269436B2

公开(公告)日：2016-02-23

申请号：US14133011

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Sreenivas Mandava ,  Brian S. Morris ,  Suneeta Sah ,  Roy M. Stevens ,  Ted Rossin ,  Mathew W. Stefaniw ,  John H. Crawford

IPC: G11C7/02 ,  G11C11/406 ,  G06F12/10 ,  G11C14/00

CPC classification number: G11C14/0009 ,  G06F12/10 ,  G06F2212/1032 ,  G11C7/02 ,  G11C11/406

Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

Abstract translation: 公开了用于基于侵入者行的逻辑地址和与易失性存储器相关联的地址转换方案来确定易失性存储器的一个或多个受害行的逻辑地址的示例。 其他的例子被描述和要求保护。

公开(公告)号：US11755486B2

公开(公告)日：2023-09-12

申请号：US17236692

申请日：2021-04-21

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/00 ,  G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42 ,  G06F12/0806 ,  G06F12/0808

CPC classification number: G06F12/084 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

公开(公告)号：US10007606B2

公开(公告)日：2018-06-26

申请号：US15085599

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Vedaraman Geetha ,  Brian S. Morris ,  Binata Bhattacharyya ,  Massimo Sutera

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0811

CPC classification number: G06F12/0831 ,  G06F12/0811 ,  G06F2212/283 ,  G06F2212/621

Abstract: Electronic circuitry of a computing system is described where the computing system includes a multi-level system memory where the multi-level system memory includes a near memory cache. The computing system directs system memory access requests whose addresses map to a same near memory cache slot to a same home caching agent so that the same home caching agent can characterize individual cache lines as inclusive or non-inclusive before forwarding the requests to a system memory controller, and where the computing system directs other system memory access requests to the system memory controller without passing the other requests through a home caching agent. The electronic circuitry is to modify the respective original addresses of the other requests to include a special code that causes the other system memory access requests to map to a specific pre-determined set of slots within the near memory cache.

公开(公告)号：US09934143B2

公开(公告)日：2018-04-03

申请号：US14038659

申请日：2013-09-26

Applicant: Intel Corporation

Inventor： Kuljit S. Bains ,  Suneeta Sah ,  John H. Crawford ,  Brian S. Morris

IPC: G06F13/12 ,  G06F12/06 ,  G06F12/02

CPC classification number: G06F12/06 ,  G06F12/0292 ,  G06F12/0638

Abstract: A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device.

公开(公告)号：US20170185473A1

公开(公告)日：2017-06-29

申请号：US14757905

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Debaleena Das ,  Rajat Agarwal ,  Brian S. Morris

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/1064

Abstract: Provided are an apparatus and method to store data from a cache line at locations having errors in a sparing directory. In response to a write operation having write data for locations in one of the cache lines, the write data for a location in the cache line having an error is written to an entry in a sparing directory including an address of the cache line.