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    High voltage three-dimensional devices having dielectric liners
    2.
    发明授权
    High voltage three-dimensional devices having dielectric liners 有权

    公开(公告)号：US12136628B2

    公开(公告)日：2024-11-05

    申请号：US18538795

    申请日：2023-12-13

    Applicant: Intel Corporation

    Inventor： Walid M. Hafez ,  Jeng-Ya D. Yeh ,  Curtis Tsai ,  Joodong Park ,  Chia-Hong Jan ,  Gopinath Bhimarasetti

    IPC: H01L27/12 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

    Abstract: High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.

    Gate endcap architectures having relatively short vertical stack
    6.
    发明授权
    Gate endcap architectures having relatively short vertical stack 有权

    公开(公告)号：US11563000B2

    公开(公告)日：2023-01-24

    申请号：US16830120

    申请日：2020-03-25

    Applicant: Intel Corporation

    Inventor： Sairam Subramanian ,  Walid M. Hafez ,  Hsu-Yu Chang ,  Chia-Hong Jan

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

    Abstract: Gate endcap architectures having relatively short vertical stack, and methods of fabricating gate endcap architectures having relatively short vertical stack, are described. In an example, an integrated circuit structure includes a first semiconductor fin along a first direction. A second semiconductor fin is along the first direction. A trench isolation material is between the first semiconductor fin and the second semiconductor fin. The trench isolation material has an uppermost surface below a top of the first and second semiconductor fins. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin and is along the first direction. The gate endcap isolation structure is on the uppermost surface of the trench isolation material.

    Transistor with dual-gate spacer
    9.
    发明授权
    Transistor with dual-gate spacer 有权

    公开(公告)号：US10535747B2

    公开(公告)日：2020-01-14

    申请号：US15778306

    申请日：2015-12-23

    Applicant: INTEL CORPORATION

    Inventor： En-Shao Liu ,  Joodong Park ,  Chen-Guan Lee ,  Chia-Hong Jan

    IPC: H01L29/49 ,  H01L21/28 ,  H01L21/764 ,  H01L29/78 ,  H01L29/66

    Abstract: Techniques are disclosed for forming a transistor with one or more additional gate spacers. The additional spacers may be formed between the gate and original gate spacers to reduce the parasitic coupling between the gate and the source/drain, for example. In some cases, the additional spacers may include air gaps and/or dielectric material (e.g., low-k dielectric material). In some cases, the gate may include a lower portion and an upper portion. In some such cases, the lower portion of the gate may be narrower in width between the original gate spacers than the upper portion of the gate, which may be as a result of the additional spacers being located between the lower portion of the gate and the original gate spacers. In some such cases, the gate may approximate a “T” shape or various derivatives of that shape such as -shape or -shape, for example.

    Dual height glass for finFET doping
    10.
    发明授权
    Dual height glass for finFET doping 有权

    公开(公告)号：US10304681B2

    公开(公告)日：2019-05-28

    申请号：US15573458

    申请日：2015-06-22

    Applicant: Intel Corporation

    Inventor： Chen-Guan Lee ,  Lu Yang ,  Joodong Park ,  Chia-Hong Jan

    IPC: H01L29/78 ,  H01L21/225 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06

    Abstract: Dual height glass is described for doping a fin of a field effect transistor structure in an integrated circuit. In one example, a method includes applying a glass layer over a fin of a FinFET structure, the fin having a source/drain region and a gate region, applying a polysilicon layer over the gate region, removing a portion of the glass layer from the source/drain region after applying the polysilicon, and thermally annealing the glass to drive dopants into the fin, and applying an epitaxial layer over the source/drain region.

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