公开(公告)号：US11688792B2

公开(公告)日：2023-06-27

申请号：US17526986

申请日：2021-11-15

申请人： Intel Corporation

发明人： Sairam Subramanian ,  Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768

CPC分类号： H01L29/66545 ,  H01L21/762 ,  H01L21/76895 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

摘要： Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US11205708B2

公开(公告)日：2021-12-21

申请号：US15943556

申请日：2018-04-02

申请人： Intel Corporation

发明人： Sairam Subramanian ,  Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/768

摘要： Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.

公开(公告)号：US11562999B2

公开(公告)日：2023-01-24

申请号：US16147733

申请日：2018-09-29

申请人： Intel Corporation

发明人： Roman Olac-Vaw ,  Nick Lindert ,  Chia-Hong Jan ,  Walid Hafez

IPC分类号： H01L27/06 ,  H01L27/07 ,  H01L49/02 ,  H01L29/51 ,  H01L29/78 ,  H01L21/027 ,  H01L29/66 ,  H01L23/522 ,  H01L23/00

摘要： A method for fabricating a semiconductor structure includes forming a plurality of semiconductor fins protruding through a trench isolation region above a substrate. A first gate structure is formed over a first of the plurality of semiconductor fins. A second gate structure is formed over a second of the plurality of semiconductor fins. A gate edge isolation structure is formed laterally between and in contact with the first gate structure and the second gate structure, the gate edge isolation structure on the trench isolation region and extending above an uppermost surface of the first gate structure and the second gate structure. A precision resistor is formed on the gate edge isolation structure, wherein the precision resistor and the first gate structure and second gate structure comprise a same material layer.

公开(公告)号：US11605632B2

公开(公告)日：2023-03-14

申请号：US17529029

申请日：2021-11-17

申请人： Intel Corporation

发明人： Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon ,  Sairam Subramanian

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L23/528

摘要： Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US11538937B2

公开(公告)日：2022-12-27

申请号：US16240166

申请日：2019-01-04

申请人： Intel Corporation

发明人： Leonard Guler ,  Nick Lindert ,  Biswajeet Guha ,  Swaminathan Sivakumar ,  Tahir Ghani

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02

摘要： Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

公开(公告)号：US10541143B2

公开(公告)日：2020-01-21

申请号：US16081404

申请日：2016-03-30

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Nick Lindert

IPC分类号： H01L21/308 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66

摘要： Methods and architectures for self-aligned build-up of patterned features. An initial patterned feature aspect ratio may be maintained or increased, for example to mitigate erosion of the feature during one or more subtractive device fabrication processes. A patterned feature height may be increased without altering an effective spacing between adjacent features that may be further relied upon, for example to further pattern an underlying material. A patterned feature may be conformally capped with a material, such as a metal or dielectric, in a self-aligned manner, for example to form a functional device layer on an initial pattern having a suitable space width-to-line height aspect ratio without the use of a masked etch to define the cap.

公开(公告)号：US20190096685A1

公开(公告)日：2019-03-28

申请号：US16081404

申请日：2016-03-30

申请人： Intel Corporation

发明人： Leonard P. Guler ,  Nick Lindert

IPC分类号： H01L21/308 ,  H01L21/02 ,  H01L21/768 ,  H01L29/66

CPC分类号： H01L21/3085 ,  H01L21/02123 ,  H01L21/76885 ,  H01L29/66545

摘要： Methods and architectures for self-aligned build-up of patterned features. An initial patterned feature aspect ratio may be maintained or increased, for example to mitigate erosion of the feature during one or more subtractive device fabrication processes. A patterned feature height may be increased without altering an effective spacing between adjacent features that may be further relied upon, for example to further pattern an underlying material. A patterned feature may be conformally capped with a material, such as a metal or dielectric, in a self-aligned manner, for example to form a functional device layer on an initial pattern having a suitable space width-to-line height aspect ratio without the use of a masked etch to define the cap.

公开(公告)号：US09972541B2

公开(公告)日：2018-05-15

申请号：US15328473

申请日：2014-08-29

申请人： Intel Corporation

发明人： Joseph M. Steigerwald ,  Nick Lindert

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L29/417 ,  H01L29/78 ,  H01L21/304 ,  H01L21/308 ,  H01L23/535 ,  H01L29/66

CPC分类号： H01L21/823475 ,  H01L21/304 ,  H01L21/3085 ,  H01L21/823431 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2224/16225 ,  H01L2924/15311

摘要： Embodiments of the present disclosure describe techniques for filling a high aspect ratio, narrow structure with multiple metal layers and associated configurations. In one embodiment, an apparatus includes a transistor structure comprising a semiconductor material, a dielectric material having a recess defined over the transistor structure, the recess having a height in a first direction, an electrode terminal disposed in the recess and coupled with the transistor structure, wherein a first portion of the electrode terminal comprises a first metal in direct contact with the transistor structure and a second portion of the electrode terminal comprises a second metal disposed on the first portion and wherein an interface between the first portion and the second portion is planar and extends across the recess in a second direction that is substantially perpendicular to the first direction. Other embodiments may be described and/or claimed.

公开(公告)号：US11217582B2

公开(公告)日：2022-01-04

申请号：US15941647

申请日：2018-03-30

申请人： Intel Corporation

发明人： Walid M. Hafez ,  Sridhar Govindaraju ,  Mark Liu ,  Szuya S. Liao ,  Chia-Hong Jan ,  Nick Lindert ,  Christopher Kenyon ,  Sairam Subramanian

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L23/528 ,  H01L29/06 ,  H01L21/8234

摘要： Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US10109628B2

公开(公告)日：2018-10-23

申请号：US15024258

申请日：2013-12-18

申请人： INTEL CORPORATION

发明人： Anand S. Murthy ,  Nick Lindert ,  Glenn A. Glass

IPC分类号： H01L29/78 ,  H01L29/786 ,  H01L27/092 ,  H01L21/265 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/10 ,  H01L29/165

摘要： Techniques are disclosed for improving gate control over the channel of a transistor, by increasing the effective electrical gate length (Leff) through deposition of a gate control layer (GCL) at the interfaces of the channel with the source and drain regions. The GCL is a nominally undoped layer (or substantially lower doped layer, relative to the heavily doped S/D fill material) that can be deposited when forming a transistor using replacement S/D deposition. The GCL can be selectively deposited in the S/D cavities after such cavities have been formed and before the heavily doped S/D fill material is deposited. In this manner, the GCL decreases the source and drain underlap (Xud) with the gate stack and further separates the heavily doped source and drain regions. This, in turn, increases the effective electrical gate length (Leff) and improves the control that the gate has over the channel.