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    Sam assisted selective e-less plating on packaging materials
    2.
    发明授权
    Sam assisted selective e-less plating on packaging materials 有权

    公开(公告)号：US10697065B2

    公开(公告)日：2020-06-30

    申请号：US15769699

    申请日：2016-08-08

    Applicant: Intel Corporation

    Inventor： Fay Hua ,  Aranzazu Maestre Caro

    IPC: H05K3/46 ,  C23C18/20 ,  H01L21/48 ,  C23C18/16

    Abstract: A method including activating an area of a polymer layer on a substrate with electromagnetic radiation; modifying the activated area; forming a self-assembled monolayer on the modified active area; reacting the self-assembled monolayer with the self-assembled monolayer; and reacting the self-assembled monolayer with a conductive material. A method including activating an area of a polymer dielectric layer on a substrate with electromagnetic radiation, the area selected for an electrically conductive line; modifying the activated area; forming a self-assembled monolayer on the modified active area; reacting the self-assembled monolayer with a catalyst; and electroless plating a conductive material on the self-assembled monolayer.

    Techniques for die stacking and associated configurations
    4.
    发明授权
    Techniques for die stacking and associated configurations 有权

    公开(公告)号：US11222863B2

    公开(公告)日：2022-01-11

    申请号：US16080989

    申请日：2016-04-01

    Applicant: Intel Corporation

    Inventor： Fay Hua ,  Christopher M. Pelto ,  Valluri R. Rao ,  Mark T. Bohr ,  Johanna M. Swan

    IPC: H01L23/00 ,  H01L21/02 ,  H01L21/768 ,  H01L21/78 ,  H01L25/065 ,  H01L25/00

    Abstract: Embodiments of the present disclosure describe techniques for fabricating a stacked integrated circuit (IC) device. A first wafer that includes a plurality of first IC dies may be sorted to identify first known good dies of the plurality of first IC dies. The first wafer may be diced to singulate the first IC dies. A second wafer that includes a plurality of second IC dies may be sorted to identify second know good dies of the plurality of second IC dies. The first known good dies may be bonded to respective second known good dies of the second wafer. In some embodiments, the first known good dies may be thinned after bonding the first know good dies to the second wafer. Other embodiments may be described and/or claimed.

    DEVICE WITH OUT-PLANE INDUCTORS
    7.
    发明申请
    DEVICE WITH OUT-PLANE INDUCTORS 审中-公开

    公开(公告)号：US20200082969A1

    公开(公告)日：2020-03-12

    申请号：US16616387

    申请日：2017-06-28

    Applicant: Intel Corporation

    Inventor： Fay Hua ,  Sidharth Dalmia ,  Zhichao Zhang

    IPC: H01F27/28 ,  H01L23/522 ,  H01L23/498 ,  H01L23/58 ,  H01L21/48 ,  H01L23/00 ,  H01F41/04

    Abstract: An apparatus is provided which comprises: a planar dielectric surface, two or more conductive leads on the surface, the conductive leads extending away from the substrate surface, two or more conductive traces on the surface between the conductive leads, the traces substantially parallel to each other, and a wire coupling a first end of a first conductive trace to an opposite end of an adjacent second conductive trace, the wire extending away from the surface. Other embodiments are also disclosed and claimed.

    Solder contacts for socket assemblies
    8.
    发明授权
    Solder contacts for socket assemblies 有权

    公开(公告)号：US10321573B2

    公开(公告)日：2019-06-11

    申请号：US15855808

    申请日：2017-12-27

    Applicant: INTEL CORPORATION

    Inventor： Fay Hua ,  Hong Xie ,  Gregorio R. Murtagian ,  Amit Abraham ,  Alan C. McAllister ,  Ting Zhong

    IPC: H05K1/11 ,  H05K3/40 ,  H05K1/18 ,  H01R12/52 ,  H01L23/498 ,  H01R33/76 ,  H05K3/34

    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.

    Device with out-plane inductors
    10.
    发明授权
    Device with out-plane inductors 有权

    公开(公告)号：US11282633B2

    公开(公告)日：2022-03-22

    申请号：US16616387

    申请日：2017-06-28

    Applicant: Intel Corporation

    Inventor： Fay Hua ,  Sidharth Dalmia ,  Zhichao Zhang

    IPC: H01F27/28 ,  H01F41/04 ,  H01L21/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/58 ,  H01L23/00

    Abstract: An apparatus is provided which comprises: a planar dielectric surface, two or more conductive leads on the surface, the conductive leads extending away from the substrate surface, two or more conductive traces on the surface between the conductive leads, the traces substantially parallel to each other, and a wire coupling a first end of a first conductive trace to an opposite end of an adjacent second conductive trace, the wire extending away from the surface. Other embodiments are also disclosed and claimed.

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