公开(公告)号：US12255234B2

公开(公告)日：2025-03-18

申请号：US18409509

申请日：2024-01-10

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L31/109

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US11923421B2

公开(公告)日：2024-03-05

申请号：US17869622

申请日：2022-07-20

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Glenn Glass ,  Anand Murthy ,  Harold Kennel ,  Jack T. Kavalieros ,  Tahir Ghani ,  Ashish Agrawal ,  Seung Hoon Sung

IPC: H01L31/072 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/165 ,  H01L31/109

CPC classification number: H01L29/165 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having germanium-based channels are described. In an example, an integrated circuit structure includes a fin having a lower silicon portion, an intermediate germanium portion on the lower silicon portion, and a silicon germanium portion on the intermediate germanium portion. An isolation structure is along sidewalls of the lower silicon portion of the fin. A gate stack is over a top of and along sidewalls of an upper portion of the fin and on a top surface of the isolation structure. A first source or drain structure is at a first side of the gate stack. A second source or drain structure is at a second side of the gate stack.

公开(公告)号：US20230178658A1

公开(公告)日：2023-06-08

申请号：US17540560

申请日：2021-12-02

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Glenn Glass ,  Anand Murthy ,  Rushabh Shah

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0665 ,  H01L29/42392 ,  H01L29/78618 ,  H01L21/0259 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66742

Abstract: A semiconductor structure includes a body including semiconductor material, and a gate structure at least in part wrapped around the body. The semiconductor structure further includes a source region and a drain region, the body laterally extending between the source and drain regions. The body has a middle region between first and second tip regions. In an example, the source region at least in part wraps around the first tip region of the body, and/or the drain region at least in part wraps around the second tip region of the body. In another example, the body includes a core structure and a peripheral structure (e.g., cladding or layer that wraps around the core structure in the middle region of the body) that is compositionally different from the core structure. The body can be, for instance, a nanoribbon, nanosheet, or nanowire or a gate-all-around device or a forksheet device.

公开(公告)号：US11527612B2

公开(公告)日：2022-12-13

申请号：US16146778

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Anand Murthy ,  Biswajeet Guha ,  Dax M. Crum ,  Sean Ma ,  Tahir Ghani ,  Susmita Ghose ,  Stephen Cea ,  Rishabh Mehandru

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/285 ,  H01L21/306 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78 ,  H01L21/683

Abstract: Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.

公开(公告)号：US11515407B2

公开(公告)日：2022-11-29

申请号：US16232535

申请日：2018-12-26

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Paul Fischer ,  Anand Murthy ,  Walid Hafez

IPC: H01L29/778 ,  H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L27/092 ,  H01L21/8252 ,  H01L29/66 ,  H01L21/306 ,  H01L23/00

Abstract: An integrated circuit structure comprises a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region include a group III-N semiconductor material, wherein the relaxed buffer stack comprises a plurality of AlGaN material layers and a buffer stack is located over over the plurality of AlGaN material layers, wherein the buffer stack comprises the group III-N semiconductor material and has a thickness of less than approximately 25 nm. A back barrier is in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al. A polarization stack over the relaxed buffer stack.

公开(公告)号：US20200091287A1

公开(公告)日：2020-03-19

申请号：US16131520

申请日：2018-09-14

Applicant: INTEL CORPORATION

Inventor： Glenn Glass ,  Anand Murthy ,  Cory Bomberger ,  Tahir Ghani ,  Jack Kavalieros ,  Siddharth Chouksey ,  Seung Hoon Sung ,  Biswajeet Guha ,  Ashish Agrawal

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8238

Abstract: A semiconductor structure has a substrate including silicon and a layer of relaxed buffer material on the substrate with a thickness no greater than 300 nm. The buffer material comprises silicon and germanium with a germanium concentration from 20 to 45 atomic percent. A source and a drain are on top of the buffer material. A body extends between the source and drain, where the body is monocrystalline semiconductor material comprising silicon and germanium with a germanium concentration of at least 30 atomic percent. A gate structure is wrapped around the body.

公开(公告)号：US11004978B2

公开(公告)日：2021-05-11

申请号：US16785431

申请日：2020-02-07

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Karthik Jambunathan ,  Anand Murthy ,  Chandra Mohapatra ,  Seiyon Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.

公开(公告)号：US20200176601A1

公开(公告)日：2020-06-04

申请号：US16785431

申请日：2020-02-07

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Karthik Jambunathan ,  Anand Murthy ,  Chandra Mohapatra ,  Seiyon Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/165

Abstract: Methods of forming germanium channel structure are described. An embodiment includes forming a germanium fin on a substrate, wherein a portion of the germanium fin comprises a germanium channel region, forming a gate material on the germanium channel region, and forming a graded source/drain structure adjacent the germanium channel region. The graded source/drain structure comprises a germanium concentration that is higher adjacent the germanium channel region than at a source/drain contact region.

公开(公告)号：US20180358436A1

公开(公告)日：2018-12-13

申请号：US15778724

申请日：2015-12-24

Applicant: Intel Corporation

Inventor： Karthik Jambunathan ,  Glenn Glass ,  Anand Murthy ,  Jun Sung Kang ,  Seiyon Kim

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L29/06 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78 ,  H01L29/78696

Abstract: Methods of forming self-aligned nanowire spacer structures are described. An embodiment includes forming a channel structure comprising a first nanowire and a second nanowire. Source/drain structures are formed adjacent the channel structure, wherein a liner material is disposed on at least a portion of the sidewalls of the source/drain structures. A nanowire spacer structure is formed between the first and second nanowires, wherein the nanowire spacer comprises an oxidized portion of the liner.

公开(公告)号：US12206027B2

公开(公告)日：2025-01-21

申请号：US18228139

申请日：2023-07-31

Applicant: Intel Corporation

Inventor： Glenn Glass ,  Anand Murthy ,  Biswajeet Guha ,  Tahir Ghani ,  Susmita Ghose ,  Zachary Geiger

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.