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    Double rounded combined floating-point multiply and add
    1.
    发明授权
    Double rounded combined floating-point multiply and add 有权

    公开(公告)号：US09477441B2

    公开(公告)日：2016-10-25

    申请号：US14948943

    申请日：2015-11-23

    Applicant: Intel Corporation

    Inventor： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

    IPC: G06F7/38 ,  G06F7/487 ,  G06F7/483 ,  G06F7/544 ,  G06F7/485 ,  G06F7/499

    CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

    Abstract: Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

    INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION
    2.
    发明申请
    INSTRUCTION AND LOGIC FOR BULK REGISTER RECLAMATION 审中-公开
    大容量存储器重新引导的指令和逻辑

    公开(公告)号：US20160092222A1

    公开(公告)日：2016-03-31

    申请号：US14496113

    申请日：2014-09-25

    Applicant: Intel Corporation

    Inventor： David Pardo Keppel ,  Denis M. Khartikov ,  Fernando LaTorre ,  Marc Lupon ,  Grigorios Magklis ,  Naveen Neelakantam ,  Georgios Tournavitis ,  Polychronis Xekalakis

    IPC: G06F9/30

    CPC classification number: G06F9/30185 ,  G06F9/384 ,  G06F9/3857

    Abstract: A processor includes a front end, a decoder, an allocator, and a retirement unit. The decoder includes logic to identify an end-of-live-range (EOLR) indicator. The EOLR indicator specifies an architectural register and a location in code for which the architectural register is unused. The allocator includes logic to scan for a mapping of the architectural register to a physical register, based upon the EOLR indicator. The allocator also includes logic to generate a request to disassociate the architectural register from the physical register. The retirement unit includes logic to disassociate the architectural register from the physical register.

    Abstract translation: 处理器包括前端，解码器，分配器和退休单元。 解码器包括用于识别终点范围（EOLR）指示符的逻辑。 EOLR指示符指定体系结构寄存器和不使用体系结构寄存器的代码中的位置。 分配器包括基于EOLR指示器扫描架构寄存器到物理寄存器的映射的逻辑。 分配器还包括生成用于将体系结构寄存器与物理寄存器取消关联的请求的逻辑。 退休单位包括将架构寄存器与物理寄存器取消关联的逻辑。

    DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD
    3.
    发明申请
    DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD 有权
    双重圆形组合浮点数乘法和加法

    公开(公告)号：US20160077802A1

    公开(公告)日：2016-03-17

    申请号：US14948943

    申请日：2015-11-23

    Applicant: Intel Corporation

    Inventor： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

    IPC: G06F7/487 ,  G06F7/499 ,  G06F7/485

    CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

    Abstract: Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

    Abstract translation: 公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。 实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。 所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数， 基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。 分别使用溢出检测选择最终结果。

    DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD
    5.
    发明申请
    DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD 审中-公开
    双重圆形组合浮点数乘法和加法

    公开(公告)号：US20170039033A1

    公开(公告)日：2017-02-09

    申请号：US15332721

    申请日：2016-10-24

    Applicant: Intel Corporation

    Inventor： Sridhar Samudrala ,  Grigorios Magklis ,  Marc Lupon ,  David R. Ditzel

    IPC: G06F7/487 ,  G06F7/499 ,  G06F7/544 ,  G06F7/485

    CPC classification number: G06F7/4876 ,  G06F7/483 ,  G06F7/485 ,  G06F7/4991 ,  G06F7/49915 ,  G06F7/5443 ,  G06F2207/4802

    Abstract: Methods, apparatus, instructions and logic are disclosed providing double rounded combined floating-point multiply and add functionality as scalar or vector SIMD instructions or as fused micro-operations. Embodiments include detecting floating-point (FP) multiplication operations and subsequent FP operations specifying as source operands results of the FP multiplications. The FP multiplications and the subsequent FP operations are encoded as combined FP operations including rounding of the results of FP multiplication followed by the subsequent FP operations. The encoding of said combined FP operations may be stored and executed as part of an executable thread portion using fused-multiply-add hardware that includes overflow detection for the product of FP multipliers, first and second FP adders to add third operand addend mantissas and the products of the FP multipliers with different rounding inputs based on overflow, or no overflow, in the products of the FP multiplier. Final results are selected respectively using overflow detection.

    Abstract translation: 公开了提供双向组合浮点乘法和附加功能作为标量或向量SIMD指令或作为融合微操作的方法，装置，指令和逻辑。 实施例包括检测浮点（FP）乘法运算和指定作为FP乘法的源操作数结果的后续FP操作。 FP乘法和随后的FP操作被编码为组合FP操作，包括对FP乘法的结果进行舍入，随后是随后的FP操作。 所述组合FP操作的编码可以作为可执行线程部分的一部分使用融合乘法硬件来存储和执行，所述融合乘法加法器包括用于FP乘法器的乘积的溢出检测，第一和第二FP加法器来添加第三操作数加法尾数， 基于FP乘法器产品中溢出或不溢出的FP乘法器的不同舍入输入的产品。 分别使用溢出检测选择最终结果。

    COMBINED FLOATING POINT MULTIPLIER ADDER WITH INTERMEDIATE ROUNDING LOGIC
    6.
    发明申请
    COMBINED FLOATING POINT MULTIPLIER ADDER WITH INTERMEDIATE ROUNDING LOGIC 有权
    具有中间圆形逻辑的组合浮点点加法器

    公开(公告)号：US20140281419A1

    公开(公告)日：2014-09-18

    申请号：US13840363

    申请日：2013-03-15

    Applicant: Intel Corporation

    Inventor： Marc Lupon ,  Grigorios Magklis ,  Sridhar Samudrala ,  Raul Martinez ,  Kyriakos A. Stavrou ,  Enric Gibert Codina

    IPC: G06F9/38

    CPC classification number: G06F9/3861 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/45508

    Abstract: An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated by the fusion code may be monitored and at least a portion of the code region instructions may be re-translated to eliminate some or all fusion code if CMA intermediate rounding exceptions exceed a threshold.

    Abstract translation: 错误处理方法包括识别符合累积乘法（CMA）优化的代码区域并将代码区域指令转换为解释器代码指令，其可以包括将代码区域指令中的乘法加法指令的序列转换成包括CMA指令的融合代码。 可以监视由融合码产生的浮点（FP）异常，并且如果CMA中间舍入异常超过阈值，则可以重新转换码区指令的至少一部分以消除一些或全部融合码。

    Combined floating point multiplier adder with intermediate rounding logic
    8.
    发明授权
    Combined floating point multiplier adder with intermediate rounding logic 有权
    具有中间舍入逻辑的组合浮点乘法器加法器

    公开(公告)号：US09389871B2

    公开(公告)日：2016-07-12

    申请号：US13840363

    申请日：2013-03-15

    Applicant: Intel Corporation

    Inventor： Marc Lupon ,  Grigorios Magklis ,  Sridhar Samudrala ,  Raul Martinez ,  Kyriakos A. Stavrou ,  Enric Gibert Codina

    IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455

    CPC classification number: G06F9/3861 ,  G06F9/3001 ,  G06F9/3017 ,  G06F9/45508

    Abstract: An error handling method includes identifying a code region eligible for cumulative multiply add (CMA) optimization and translating code region instructions into interpreter code instructions, which may include translating sequences of multiply add instructions in the code region instructions into fusion code including CMA instructions. Floating point (FP) exceptions generated by the fusion code may be monitored and at least a portion of the code region instructions may be re-translated to eliminate some or all fusion code if CMA intermediate rounding exceptions exceed a threshold.

    Abstract translation: 错误处理方法包括识别符合累积乘法（CMA）优化的代码区域并将代码区域指令转换为解释器代码指令，其可以包括将代码区域指令中的乘法加法指令的序列转换成包括CMA指令的融合代码。 可以监视由融合码产生的浮点（FP）异常，并且如果CMA中间舍入异常超过阈值，则可以重新转换码区指令的至少一部分以消除一些或全部融合码。

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