公开(公告)号：US20200334161A1

公开(公告)日：2020-10-22

申请号：US16921685

申请日：2020-07-06

Applicant: Intel Corporation

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC: G06F12/0875 ,  G06N3/063 ,  G06N3/04 ,  G06F3/06 ,  G06F8/41 ,  G06F9/455

Abstract: The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.

公开(公告)号：US20160202954A1

公开(公告)日：2016-07-14

申请号：US14912895

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： SASIKANTH MANIPATRUNI ,  DMITRI NIKONOV ,  IAN YOUNG

IPC: G06F7/58 ,  H01L43/08 ,  H01L43/10 ,  G06F1/16

CPC classification number: H01L43/08 ,  B82Y25/00 ,  G06F1/1613 ,  G06F7/588 ,  H01F10/3254 ,  H01F10/3272 ,  H01L43/10

Abstract: Described is an apparatus for a voltage controlled nano-magnetic random number generator. The apparatus comprises: a free ferromagnetic layer; a fixed ferromagnetic layer positioned in a non-collinear direction relative to the free ferromagnet layer; and a first terminal coupled to the free ferromagnetic layer, the first terminal to provide a bias voltage to the free ferromagnetic layer. Described is also an integrated circuit comprising: a random number generator including a magnetic tunnel junction (MTJ) device with non-collinearly positioned free and fixed ferromagnetic layers; and a circuit to provide an adjustable bias voltage to the free ferromagnetic layer, the circuit to control variance of current generated by the random number generator.

Abstract translation: 描述了一种用于电压控制的纳米磁性随机数发生器的装置。 该装置包括：自由铁磁层; 相对于游离铁磁体层位于非共线方向的固定铁磁层; 以及耦合到所述自由铁磁层的第一端子，所述第一端子为所述自由铁磁层提供偏置电压。 还描述了一种集成电路，包括：随机数发生器，其包括具有非共线定位的自由和固定的铁磁层的磁性隧道结（MTJ）装置; 以及向自由铁磁层提供可调偏置电压的电路，该电路控制由随机数发生器产生的电流的变化。

公开(公告)号：US20170345896A1

公开(公告)日：2017-11-30

申请号：US15525885

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： RASEONG KIM ,  UYGAR AVCI ,  IAN YOUNG

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L29/786 ,  B82Y10/00

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Field effect transistor structures are described that are formed using germanium nanowires. In one example, the structure has a germanium nanowire formed on a substrate along a predetermined confinement orientation, a first doped region of the nanowire at a first end of the nanowire to define a source, a second doped region of the nanowire at a second end of the nanowire to define a drain, and a gate dielectric formed over the nanowire between the source and the drain.

公开(公告)号：US20160042778A1

公开(公告)日：2016-02-11

申请号：US14780489

申请日：2013-06-21

Applicant: INTEL CORPORATION

Inventor： SASIKANTH MANIPATRUNI ,  DMITRI NIKONOV ,  IAN YOUNG

IPC: G11C11/16 ,  H01L43/06 ,  H01L27/22 ,  H01L43/12

CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/18 ,  H01L27/226 ,  H01L27/228 ,  H01L43/06 ,  H01L43/08 ,  H01L43/12

Abstract: Described is an apparatus 1T-1 Magnetic Tunnel Junction (MTJ) Spin Hall Magnetic Random Access Memory (MRAM) bit-cell and array, and method of forming such. The apparatus comprises: a select line; an interconnect with Spin Hall Effect (SHE) material, the interconnect coupled to a write bit line; a transistor coupled to the select line and the interconnect, the transistor controllable by a word line; and a MTJ device having a free magnetic layer coupled to the interconnect.

Abstract translation: 描述了一种装置1T-1磁隧道结（MTJ）旋转磁体随机存取存储器（MRAM）位单元和阵列及其形成方法。 该装置包括：选择线; 与旋转霍尔效应（SHE）材料的互连，耦合到写位线的互连; 耦合到选择线和互连的晶体管，晶体管可由字线控制; 以及具有耦合到互连的自由磁性层的MTJ装置。