公开(公告)号：US20190035673A1

公开(公告)日：2019-01-31

申请号：US16077555

申请日：2016-03-31

Applicant: Intel Corporation

Inventor： Ebony L. Mays ,  Jeanne L. Luce ,  Elizabeth Mallon

IPC: H01L21/762 ,  H01L21/02 ,  H01L29/78

Abstract: An embodiment includes a semiconductor apparatus comprising: a trench with an aspect ratio of at least 7:1 (height:width); and a dielectric included in the trench; wherein the dielectric: (a) includes carbon and at least one of silicon nitride and silicon carbide, and (b) does not include an oxide. Other embodiments are described herein.

公开(公告)号：US09406547B2

公开(公告)日：2016-08-02

申请号：US14139964

申请日：2013-12-24

Applicant: INTEL CORPORATION

Inventor： Ritesh Jhaveri ,  Jeanne L. Luce ,  Sang-Won Park ,  Dennis G. Hanken

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02222 ,  H01L21/02274 ,  H01L21/02323 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/02343 ,  H01L21/02345 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate.

Abstract translation: 公开了用于使用可流动介电材料提供半导体翅片的沟槽隔离的技术。 根据一些实施例，可流动电介质可以例如使用可流动的化学气相沉积（FCVD）工艺沉积在鳍状图案化的半导体衬底上。 可流动电介质可以流入相邻散热片之间的沟槽，其中它可以原位固化，从而根据一些实施例在衬底上形成电介质层。 通过固化，可以根据给定目标应用或最终用途的需要将可流动电介质转化为例如氧化物，氮化物和/或碳化物。 在一些实施例中，所得到的电介质层可以是基本上无缺陷的，没有或以其他方式减少接缝/空隙的量。 在固化之后，所得到的介电层可进行湿化学，热和/或等离子体处理，例如改变其介电特性，密度和/或蚀刻速率中的至少一个。

公开(公告)号：US10964800B2

公开(公告)日：2021-03-30

申请号：US16342865

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Byron Ho ,  Michael L. Hattendorf ,  Jeanne L. Luce ,  Ebony L. Mays ,  Erica J. Thompson

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L27/092 ,  H01L27/088 ,  H01L29/08 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234

Abstract: Semiconductor devices having fin-end stress-inducing features, and methods of fabricating semiconductor devices having fin-end stress-inducing features, are described. In an example, a semiconductor structure includes a semiconductor fin protruding through a trench isolation region above a substrate. The semiconductor fin has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. A gate electrode is over a region of the top surface and laterally adjacent to a region of the pair of sidewalls of the semiconductor fin. The gate electrode is between the first end and the second end of the semiconductor fin. A first dielectric plug is at the first end of the semiconductor fin. A second dielectric plug is at the second end of the semiconductor fin.

公开(公告)号：US10811251B2

公开(公告)日：2020-10-20

申请号：US16324859

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Jeanne L. Luce ,  Ebony L. Mays ,  Aravind S. Killampalli ,  Jay P. Gupta

IPC: H01L21/02 ,  C23C16/56 ,  H01L21/205 ,  H01L21/768 ,  H01L23/538 ,  H01L23/498 ,  H01L23/14

Abstract: A flowable chemical vapor deposition method including depositing a dielectric film precursor on a substrate in a flowable form; depositing an oligomerization agent on the substrate; forming a dielectric film from the dielectric film precursor; and curing the dielectric film under a pressure greater than atmospheric pressure. A method including depositing a dielectric film precursor as a liquid on a substrate in the presence of an oligomerization agent; treating the deposited dielectric film precursor to inhibit outgassing; and curing the dielectric film precursor to form a dielectric film. A method including delivering a dielectric film precursor as a vapor to a substrate including gap structures between device features; condensing the dielectric film precursor on the substrate to a liquid; flowing the liquid into the gap structures; and curing the dielectric film precursor under a pressure of 15 pounds per square inch gauge or greater.

公开(公告)号：US10998445B2

公开(公告)日：2021-05-04

申请号：US16877355

申请日：2020-05-18

Applicant: Intel Corporation

Inventor： Sameer S. Pradhan ,  Jeanne L. Luce

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234

Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

公开(公告)号：US20200279950A1

公开(公告)日：2020-09-03

申请号：US16877355

申请日：2020-05-18

Applicant: Intel Corporation

Inventor： Sameer S. Pradhan ,  Jeanne L. Luce

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/768 ,  H01L21/8234

Abstract: The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.

公开(公告)号：US10147634B2

公开(公告)日：2018-12-04

申请号：US15224987

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Ritesh Jhaveri ,  Jeanne L. Luce ,  Sang-Won Park ,  Dennis G. Hanken

IPC: H01L21/762 ,  H01L29/06 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234

Abstract: Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids. After curing, the resultant dielectric layer can undergo wet chemical, thermal, and/or plasma treatment, for instance, to modify at least one of its dielectric properties, density, and/or etch rate.