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    Technologies for accelerated QUIC packet processing with hardware offloads
    2.
    发明授权
    Technologies for accelerated QUIC packet processing with hardware offloads 有权

    公开(公告)号：US11336625B2

    公开(公告)日：2022-05-17

    申请号：US16022843

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Manasi Deval ,  Gregory Bowers

    IPC: H04L29/06 ,  H04L9/08 ,  H04L69/324 ,  H04L69/16 ,  H04L69/321 ,  H04L69/164

    Abstract: Technologies for accelerated QUIC packet processing include a computing device having a network controller. The computing device programs the network controller with an encryption key associated with a QUIC protocol connection. The computing device may pass a QUIC packet to the network controller, which encrypts a payload of the QUIC packet using the encryption key. The network controller may segment the QUIC packet into multiple segmented QUIC packets before encryption. The network controller transmits encrypted QUIC packets to a remote host. The network controller may receive encrypted QUIC packets from a remote host. The network controller decrypts the encrypted payload of received QUIC packets and may evaluate an assignment function with an entropy source in the received QUIC packets and forward the received QUIC packets to a receive queue based on the assignment function. Each receive queue may be associated with a processor core. Other embodiments are described and claimed.

    ADAPTIVE INTERRUPT MODERATION
    3.
    发明申请
    ADAPTIVE INTERRUPT MODERATION 审中-公开
    自适应中断调制

    公开(公告)号：US20150186307A1

    公开(公告)日：2015-07-02

    申请号：US14642967

    申请日：2015-03-10

    Applicant: Intel Corporation

    Inventor： Yadong Li ,  Linden Cornett ,  Manasi Deval ,  Anil Vasudevan ,  Parthasarathy Sarangam

    IPC: G06F13/24

    CPC classification number: G06F13/24 ,  H04L69/165

    Abstract: Generally, this disclosure relates to adaptive interrupt moderation. A method may include determining, by a host device, a number of connections between the host device and one or more link partners based, at least in part, on a connection identifier associated with each connection; determining, by the host device, a new interrupt rate based at least in part on a number of connections; updating, by the host device, an interrupt moderation timer with a value related to the new interrupt rate; and configuring the interrupt moderation timer to allow interrupts to occur at the new interrupt rate.

    Abstract translation: 通常，本公开涉及自适应中断调节。 方法可以包括：至少部分地基于与每个连接相关联的连接标识符，由主机设备确定主机设备与一个或多个链路伙伴之间的连接数; 由所述主机设备至少部分地基于多个连接来确定新的中断率; 通过所述主机设备更新具有与所述新中断速率相关的值的中断调节定时器; 并配置中断调节定时器以允许以新的中断速率发生中断。

    TECHNOLOGIES FOR ACCELERATED HTTP PROCESSING WITH HARDWARE ACCELERATION
    4.
    发明公开
    TECHNOLOGIES FOR ACCELERATED HTTP PROCESSING WITH HARDWARE ACCELERATION 审中-公开

    公开(公告)号：US20230421627A1

    公开(公告)日：2023-12-28

    申请号：US18202408

    申请日：2023-05-26

    Applicant: Intel Corporation

    Inventor： Parthasarathy Sarangam ,  Manasi Deval ,  Gregory Bowers

    IPC: H04L67/02 ,  H04L69/04 ,  H04L69/166 ,  H04L69/164 ,  H04L9/40

    CPC classification number: H04L67/02 ,  H04L69/04 ,  H04L69/166 ,  H04L69/164 ,  H04L63/0485 ,  H04L63/0428

    Abstract: Technologies for accelerated HTTP message processing include a computing device having a network controller. The computing device may generate an HTTP message, frame the HTTP message to generate a transport protocol packet such as a TCP/IP packet or QUIC packet, and pass the transport protocol packet to the network controller. The network controller compresses the HTTP header of the HTTP message, encrypts the compressed HTTP message, and transmits the encrypted message to a remote device. The network controller may segment the transport protocol packet into multiple segmented packets. The network controller may receive transport protocol packets that include encrypted HTTP message. The network controller decrypts the encrypted HTTP message to generate a compressed HTTP message, decompresses the HTTP message, and steers the HTTP message to a receive queue based on contents of an HTTP header. The network controller may coalesce multiple transport protocol packets. Other embodiments are described and claimed.

    Concept for Segmenting an Application Buffer into Data Packets
    6.
    发明申请
    Concept for Segmenting an Application Buffer into Data Packets 审中-公开

    公开(公告)号：US20190356589A1

    公开(公告)日：2019-11-21

    申请号：US16414814

    申请日：2019-05-17

    Applicant: Intel Corporation

    Inventor： Eliel Louzoun ,  Manasi Deval ,  Stephen Doyle ,  Noam Elati ,  Patrick Fleming ,  Gregory Bowers

    IPC: H04L12/741 ,  H04L12/861

    Abstract: An apparatus, a method and a computer program for generating data packets according to a transport protocol from an application buffer comprising a plurality of data streams is provided. The apparatus comprises an input circuit configured to receive metadata comprising at least one of information about data packet types supported by the transport protocol, information about an offset and a length of the supported data packet types, and information about possible stream header start positions, possible payload start positions and possible offsets in the data streams. Further, the apparatus comprises a parsing circuit configured to identify offsets in an application buffer as possible segmentation points based on the metadata, to segment the application buffer at the possible segmentation points into segments for data packets, and to generate data packets according to the transport protocol based on the segments. Furthermore, an apparatus, a method and a computer program for processing the application buffer is provided.

    TECHNOLOGIES FOR PACING NETWORK PACKET TRANSMISSIONS
    7.
    发明申请
    TECHNOLOGIES FOR PACING NETWORK PACKET TRANSMISSIONS 审中-公开

    公开(公告)号：US20190273693A1

    公开(公告)日：2019-09-05

    申请号：US16415023

    申请日：2019-05-17

    Applicant: Intel Corporation

    Inventor： Manasi Deval ,  Gregory J. Bowers ,  Ryan E. Hall

    IPC: H04L12/801

    Abstract: Technologies for pacing network packet transmissions include a computing device. The computing device includes a compute engine and a network interface controller (NIC). The NIC is to select a first transmit descriptor from a window of transmit descriptors. The first transmit descriptor is associated with a packet stream. The NIC is also to identify a node of a plurality of nodes of a hierarchical scheduler. The node is associated with the selected first transmit descriptor. The NIC is also to determine whether the identified node has a target amount of transmission credits available and transmit, in response to a determination that the identified node has a target amount of transmission credits available, the network packet associated with the first transmit descriptor to a target computing device.

    TECHNOLOGIES FOR ACCELERATED HTTP PROCESSING WITH HARDWARE ACCELERATION
    8.
    发明申请
    TECHNOLOGIES FOR ACCELERATED HTTP PROCESSING WITH HARDWARE ACCELERATION 审中-公开

    公开(公告)号：US20190044994A1

    公开(公告)日：2019-02-07

    申请号：US16022949

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Parthasarathy Sarangam ,  Manasi Deval ,  Gregory Bowers

    IPC: H04L29/08 ,  H04L29/06

    Abstract: Technologies for accelerated HTTP message processing include a computing device having a network controller. The computing device may generate an HTTP message, frame the HTTP message to generate a transport protocol packet such as a TCP/IP packet or QUIC packet, and pass the transport protocol packet to the network controller. The network controller compresses the HTTP header of the HTTP message, encrypts the compressed HTTP message, and transmits the encrypted message to a remote device. The network controller may segment the transport protocol packet into multiple segmented packets. The network controller may receive transport protocol packets that include encrypted HTTP message. The network controller decrypts the encrypted HTTP message to generate a compressed HTTP message, decompresses the HTTP message, and steers the HTTP message to a receive queue based on contents of an HTTP header. The network controller may coalesce multiple transport protocol packets. Other embodiments are described and claimed.

    TECHNOLOGIES FOR ACCELERATED QUIC PACKET PROCESSING WITH HARDWARE OFFLOADS
    9.
    发明申请
    TECHNOLOGIES FOR ACCELERATED QUIC PACKET PROCESSING WITH HARDWARE OFFLOADS 审中-公开

    公开(公告)号：US20190044705A1

    公开(公告)日：2019-02-07

    申请号：US16022843

    申请日：2018-06-29

    Applicant: Intel Corporation

    Inventor： Manasi Deval ,  Gregory Bowers

    IPC: H04L9/08 ,  H04L29/06 ,  H04L29/08

    Abstract: Technologies for accelerated QUIC packet processing include a computing device having a network controller. The computing device programs the network controller with an encryption key associated with a QUIC protocol connection. The computing device may pass a QUIC packet to the network controller, which encrypts a payload of the QUIC packet using the encryption key. The network controller may segment the QUIC packet into multiple segmented QUIC packets before encryption. The network controller transmits encrypted QUIC packets to a remote host. The network controller may receive encrypted QUIC packets from a remote host. The network controller decrypts the encrypted payload of received QUIC packets and may evaluate an assignment function with an entropy source in the received QUIC packets and forward the received QUIC packets to a receive queue based on the assignment function. Each receive queue may be associated with a processor core. Other embodiments are described and claimed.

    TECHNOLOGIES FOR MANAGING NETWORK STATISTIC COUNTERS
    10.
    发明申请
    TECHNOLOGIES FOR MANAGING NETWORK STATISTIC COUNTERS 审中-公开

    公开(公告)号：US20180152366A1

    公开(公告)日：2018-05-31

    申请号：US15721817

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Linden Cornett ,  Chih-Jen Chang ,  Manasi Deval ,  Parthasarathy Sarangam ,  Naru D. Sundar ,  Padma Akkiraju ,  Alexander Nguyen

    IPC: H04L12/26

    Abstract: Technologies for managing network statistic counters include a network interface controller (NIC) of a computing device configured to identify a statistic counter of and a software consumer associated with a received network packet and identify an active counter page as a function of the identified software consumer. The NIC is further configured to read a value of the statistic counter stored at a counter memory address of a corresponding counter identifier entry of the identified active counter page, increment a read value of the statistic counter, and write the incremented value of the statistic counter back to the counter memory address. Additionally, in response to detecting a notification triggering event, generating a notification message that includes a present value of the statistic counter and a present value of each of the other statistic counters of the active counter page, and transmit the generated notification message to the software consumer. Other embodiments are described herein.

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