公开(公告)号：US20190318959A1

公开(公告)日：2019-10-17

申请号：US16346305

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI ,  Marie KRYSAK

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US20220130719A1

公开(公告)日：2022-04-28

申请号：US17568648

申请日：2022-01-04

Applicant: Intel Corporation

Inventor： Kevin L. LIN ,  Robert L. BRISTOL ,  James M. BLACKWELL ,  Rami HOURANI ,  Marie KRYSAK

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/311

Abstract: Approaches based on differential hardmasks for modulation of electrobucket sensitivity for semiconductor structure fabrication, and the resulting structures, are described. In an example, a method of fabricating an interconnect structure for an integrated circuit includes forming a hardmask layer above an inter-layer dielectric (ILD) layer formed above a substrate. A plurality of dielectric spacers is formed on the hardmask layer. The hardmask layer is patterned to form a plurality of first hardmask portions. A plurality of second hardmask portions is formed alternating with the first hardmask portions. A plurality of electrobuckets is formed on the alternating first and second hardmask portions and in openings between the plurality of dielectric spacers. Select ones of the plurality of electrobuckets are exposed to a lithographic exposure and removed to define a set of via locations.

公开(公告)号：US20210082800A1

公开(公告)日：2021-03-18

申请号：US17110215

申请日：2020-12-02

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.

公开(公告)号：US20190237329A1

公开(公告)日：2019-08-01

申请号：US16316990

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Marie KRYSAK ,  Florian GSTREIN ,  Manish CHANDHOK

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/311 ,  C01G23/04 ,  C01F7/02 ,  C01G27/02 ,  C01G19/02

CPC classification number: H01L21/0332 ,  C01F7/00 ,  C01F7/02 ,  C01G19/02 ,  C01G23/04 ,  C01G25/02 ,  C01G27/02 ,  C01P2004/64 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02282 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76838 ,  H01L21/76897

Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.

公开(公告)号：US20180204760A1

公开(公告)日：2018-07-19

申请号：US15744018

申请日：2015-09-23

Applicant: Intel Corporation

Inventor： Manish CHANDHOK ,  Todd R. YOUNKIN ,  Eungnak HAN ,  Jasmeet S. (JZ) CHAWLA ,  Marie KRYSAK ,  Hui Jae YOO ,  Tristan A. TRONIC

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238

Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.

公开(公告)号：US20220093399A1

公开(公告)日：2022-03-24

申请号：US17544684

申请日：2021-12-07

Applicant: Intel Corporation

Inventor： Marie KRYSAK ,  Florian GSTREIN ,  Manish CHANDHOK

IPC: H01L21/033 ,  C01G27/02 ,  H01L21/311 ,  C01G19/02 ,  C01G23/04 ,  C01F7/02 ,  C01G25/02 ,  H01L21/02 ,  C01F7/00 ,  H01L21/768

Abstract: A dielectric composition including a metal oxide particle including a diameter of 5 nanometers or less capped with an organic ligand at at least a 1:1 ratio. A method including synthesizing metal oxide particles including a diameter of 5 nanometers or less; and capping the metal oxide particles with an organic ligand at at least a 1:1 ratio. A method including forming an interconnect layer on a semiconductor substrate; forming a first hardmask material and a different second hardmask material on the interconnect layer, wherein at least one of the first hardmask material and the second hardmask material is formed over an area of interconnect layer target for a via landing and at least one of the first hardmask material and the second hardmask material include metal oxide nanoparticles; and forming an opening to the interconnect layer selectively through one of the first hardmask material and the second hardmask material.

公开(公告)号：US20210397084A1

公开(公告)日：2021-12-23

申请号：US17464393

申请日：2021-09-01

Applicant: Intel Corporation

Inventor： James M. BLACKWELL ,  Robert L. BRISTOL ,  Marie KRYSAK ,  Florian GSTREIN ,  Eungnak HAN ,  Kevin L. LIN ,  Rami HOURANI ,  Shane M. HARLSON

IPC: G03F7/00 ,  H01L21/027 ,  H01L21/768 ,  G03F7/40

Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

公开(公告)号：US20200335434A1

公开(公告)日：2020-10-22

申请号：US16389672

申请日：2019-04-19

Applicant: Intel Corporation

Inventor： Marie KRYSAK ,  Kevin L. LIN ,  Robert BRISTOL ,  Charles H. WALLACE

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/027

Abstract: Embodiments include a substrate and a method of forming the substrate. A substrate includes an interlayer dielectric and conductive traces in the interlayer dielectric (ILD). The conductive traces may include a first conductive trace surrounded by a second and third conductive traces. The substrate also includes a photoresist block in a region of the ILD. The region may be directly surrounded by the ILD and first conductive trace, and the photoresist block may be between the first conductive trace. The photoresist block may have a top surface that is substantially coplanar to top surfaces of the ILD and conductive traces. The photoresist block may have a width substantially equal to a width of the conductive traces. The photoresist block may be in the first conductive trace and between the second and third conductive traces. The photoresist block may include a metal oxide core embedded with organic ligands.

公开(公告)号：US20190043731A1

公开(公告)日：2019-02-07

申请号：US16075555

申请日：2016-04-08

Applicant: Intel Corporation

Inventor： Robert L. BRISTOL ,  Marie KRYSAK ,  James M. BLACKWELL ,  Florian GSTREIN ,  Kent N. FRASURE

IPC: H01L21/311 ,  G03F7/004 ,  G03F7/039 ,  G03F7/20 ,  G03F7/38 ,  H01L21/027 ,  H01L21/033

Abstract: Two-stage bake photoresists with releasable quenchers for fabricating back end of line (BEOL) interconnects are described. In an example, a photolyzable composition includes an acid-deprotectable photoresist material having substantial transparency at a wavelength, a photo-acid-generating (PAG) component having substantial transparency at the wavelength, and a base-generating component having substantial absorptivity at the wavelength.

公开(公告)号：US20240071917A1

公开(公告)日：2024-02-29

申请号：US18384582

申请日：2023-10-27

Applicant: Intel Corporation

Inventor： Richard E. SCHENKER ,  Robert L. BRISTOL ,  Kevin L. LIN ,  Florian GSTREIN ,  James M. BLACKWELL ,  Marie KRYSAK ,  Manish CHANDHOK ,  Paul A. NYHUS ,  Charles H. WALLACE ,  Curtis W. WARD ,  Swaminathan SIVAKUMAR ,  Elliot N. TAN

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L27/0886 ,  H01L29/7848

Abstract: Advanced lithography techniques including sub-10 nm pitch patterning and structures resulting therefrom are described. Self-assembled devices and their methods of fabrication are described.