公开(公告)号：US20240204059A1

公开(公告)日：2024-06-20

申请号：US18080907

申请日：2022-12-14

Applicant: Intel Corporation

Inventor： Pratik KOIRALA ,  Michael S. BEUMER ,  Marko RADOSAVLJEVIC ,  Han Wui THEN

IPC: H01L29/32 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/778

CPC classification number: H01L29/32 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/7786

Abstract: Gallium nitride (GaN) with interlayers for integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon. A layer including gallium and nitrogen is above the substrate. The layer including gallium and nitrogen has an interlayer therein. The interlayer confines a plurality of defects to a lower portion of the layer including gallium and nitrogen.

公开(公告)号：US20230081460A1

公开(公告)日：2023-03-16

申请号：US17476310

申请日：2021-09-15

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Nicole K. THOMAS ,  Pratik KOIRALA ,  Nityan NAIR ,  Paul B. FISCHER

IPC: G02B6/42 ,  G06F1/16

Abstract: Gallium nitride (GaN) integrated circuit technology with optical communication is described. In an example, an integrated circuit structure includes a layer or substrate having a first region and a second region, the layer or substrate including gallium and nitrogen. A GaN-based device is in or on the first region of the layer or substrate. A CMOS-based device is over the second region of the layer or substrate. An interconnect structure is over the GaN-based device and over the CMOS-based device, the interconnect structure including conductive interconnects and vias in a dielectric layer. A photonics waveguide is over the interconnect structure, the photonics waveguide including silicon, and the photonics waveguide bonded to the dielectric layer of the interconnect structure.

公开(公告)号：US20230047449A1

公开(公告)日：2023-02-16

申请号：US17402054

申请日：2021-08-13

Applicant: Intel Corporation

Inventor： Nicole K. THOMAS ,  Samuel James BADER ,  Marko RADOSAVLJEVIC ,  Han Wui THEN ,  Pratik KOIRALA ,  Nityan NAIR

IPC: H01L27/06 ,  H01L29/20 ,  H01L29/40 ,  H01L29/778 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/02

Abstract: Gallium nitride (GaN) integrated circuit technology is described. In an example, an integrated circuit structure includes a substrate including silicon, the substrate having a top surface. A first trench is in the substrate, the first trench having a first width. A second trench is in the substrate, the second trench having a second width less than the first width. A first island is in the first trench, the first island including gallium and nitrogen and having first corner facets below the top surface of the substrate. A second island is in the second trench, the second island including gallium and nitrogen and having second corner facets below the top surface of the substrate.

公开(公告)号：US20210407997A1

公开(公告)日：2021-12-30

申请号：US16912113

申请日：2020-06-25

Applicant: Intel Corporation

Inventor： Nicole THOMAS ,  Ehren MANNEBACH ,  Cheng-Ying HUANG ,  Marko RADOSAVLJEVIC

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using a selective bottom-up approach, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a substrate. The vertical arrangement of nanowires has one or more active nanowires above one or more oxide nanowires. A first gate stack is over and around the one or more active nanowires. A second gate stack is over and around the one or more oxide nanowires.

公开(公告)号：US20210050455A1

公开(公告)日：2021-02-18

申请号：US17074251

申请日：2020-10-19

Applicant: Intel Corporation

Inventor： Van H. LE ,  Gilbert DEWEY ,  Rafael RIOS ,  Jack T. KAVALIEROS ,  Marko RADOSAVLJEVIC ,  Kent E. MILLARD ,  Marc C. FRENCH ,  Ashish AGRAWAL ,  Benjamin CHU-KUNG ,  Ryan E. ARCH

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L21/02 ,  H01L29/24 ,  H01L29/40 ,  H01L29/49

Abstract: Embodiments of the invention include non-planar InGaZnO (IGZO) transistors and methods of forming such devices. In an embodiment, the IGZO transistor may include a substrate and source and drain regions formed over the substrate. According to an embodiment, an IGZO layer may be formed above the substrate and may be electrically coupled to the source region and the drain region. Further embodiments include a gate electrode that is separated from the IGZO layer by a gate dielectric. In an embodiment, the gate dielectric contacts more than one surface of the IGZO layer. In one embodiment, the IGZO transistor is a finfet transistor. In another embodiment the IGZO transistor is a nanowire or a nanoribbon transistor. Embodiments of the invention may also include a non-planar IGZO transistor that is formed in the back end of line stack (BEOL) of an integrated circuit chip.

公开(公告)号：US20200266278A1

公开(公告)日：2020-08-20

申请号：US16279150

申请日：2019-02-19

Applicant: INTEL CORPORATION

Inventor： Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Paul B. FISCHER ,  Walid M. HAFEZ

IPC: H01L29/40 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423 ,  H01L29/778 ,  H01L21/765 ,  H01L21/28 ,  H01L29/66 ,  H01L23/66

Abstract: A semiconductor device structure having a “T-shaped” gate structure is described. A narrower first portion supports high frequency processes (e.g., gigahertz wireless communications). A second portion of the gate structure has a second width greater than the first width. Lateral extensions (sometimes referred to as “field plates), thinner and wider than the second portion, extend from the second portion. This combination of a gate structure having a narrow first portion and a wider second portion improves the performance of the semiconductor device in applications that involve both high frequency and high power consumption.

公开(公告)号：US20200227545A1

公开(公告)日：2020-07-16

申请号：US16651327

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Stephan LEUSCHNER ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/765 ,  H01L21/285 ,  H01L29/66 ,  H03F3/45 ,  H03F3/21

Abstract: Gallium nitride (GaN) transistors with source and drain field plates are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, a source field plate above the source region, and a drain field plate above the drain region.

公开(公告)号：US20200227544A1

公开(公告)日：2020-07-16

申请号：US16651326

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Stephan LEUSCHNER ,  Marko RADOSAVLJEVIC ,  Sansaptak DASGUPTA

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/765 ,  H01L21/285 ,  H01L29/66 ,  H03F3/21 ,  H03F3/45

Abstract: Gallium nitride (GaN) transistors with drain field plates and their methods of fabrication are described. In an example, a transistor includes a gallium nitride (GaN) layer above a substrate, a gate structure over the GaN layer, a source region on a first side of the gate structure, a drain region on a second side of the gate structure, the second side opposite the first side, and a drain field plate above the drain region, wherein the drain field plate is not electrically coupled to the gate structure or the source region.

公开(公告)号：US20200168634A1

公开(公告)日：2020-05-28

申请号：US16630368

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Seung Hoon SUNG ,  Ravi PILLARISETTY ,  Marko RADOSAVLJEVIC

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L21/02 ,  H01L21/383 ,  H01L29/66 ,  G05F1/56 ,  G06F1/26

Abstract: Described herein are apparatuses, systems, and methods associated with a voltage regulator circuit that includes one or more thin-film transistors (TFTs). The TFTs may be formed in the back-end of an integrated circuit. Additionally, the TFTs may include one or more unique features, such as a channel layer treated with a gas or plasma, and/or a gate oxide layer that is thicker than in prior TFTs. The one or more TFTs of the voltage regulator circuit may improve the operation of the voltage regulator circuit and free up front-end substrate area for other devices. Other embodiments may be described and claimed.

公开(公告)号：US20200066889A1

公开(公告)日：2020-02-27

申请号：US16321411

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Han Wui THEN ,  Sansaptak DASGUPTA ,  Marko RADOSAVLJEVIC

IPC: H01L29/778 ,  H01L29/08 ,  H01L29/20 ,  H01L29/40

Abstract: Embodiments of the invention include a semiconductor device and methods of forming such devices. In an embodiment, the semiconductor device includes a source region, a drain region, and a channel region formed between the source region and drain region. In an embodiment, a first interlayer dielectric (ILD) may be formed over the channel region, and a first opening is formed through the first ILD. In an embodiment, a second ILD may be formed over the first ILD, and a second opening is formed through the second ILD. Embodiments of the invention include the second opening being offset from the first opening. Embodiments may also include a gate electrode formed through the first opening and the second opening. In an embodiment, the offset between the first opening and the second opening results in the formation of a field plate and a spacer that reduces a gate length of the semiconductor device.