公开(公告)号：US20240213250A1

公开(公告)日：2024-06-27

申请号：US18088547

申请日：2022-12-24

Applicant: INTEL CORPORATION

Inventor： Shao Ming KOH ,  Sudipto NASKAR ,  Leonard P. GULER ,  Patrick MORROW ,  Richard E. SCHENKER ,  Walid M. HAFEZ ,  Charles H. WALLACE ,  Mohit K. HARAN ,  Jeanne L. LUCE ,  Dan S. LAVRIC ,  Jack T. KAVALIEROS ,  Matthew PRINCE ,  Lars LIEBMANN

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L29/0673 ,  H01L29/78696

Abstract: Embodiments disclosed herein include forksheet transistor transistors with self-aligned backbones. In an example, an integrated circuit structure includes a backbone including a lower backbone portion distinct from an upper backbone portion. A first vertical stack of nanowires is in lateral contact with a first side of the backbone. A second vertical stack of nanowires is in lateral contact with a second side of the backbone, the second side opposite the first side.

公开(公告)号：US20220238383A1

公开(公告)日：2022-07-28

申请号：US17720150

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Roman W. OLAC-VAW ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Pei-Chi LIU

IPC: H01L21/8234 ,  H01L27/12 ,  H01L21/84 ,  H01L29/78 ,  H01L21/28 ,  H01L23/528 ,  H01L27/088 ,  H01L29/49 ,  H01L21/8238

Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

公开(公告)号：US20220077145A1

公开(公告)日：2022-03-10

申请号：US17529029

申请日：2021-11-17

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON ,  Sairam SUBRAMANIAN

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/06 ,  H01L29/66 ,  H01L21/8234

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US20210280683A1

公开(公告)日：2021-09-09

申请号：US16810156

申请日：2020-03-05

Applicant: Intel Corporation

Inventor： Tanuj TRIVEDI ,  Rahul RAMASWAMY ,  Jeong Dong KIM ,  Babak FALLAHAZAD ,  Hsu-Yu CHANG ,  Ting CHANG ,  Nidhi NIDHI ,  Walid M. HAFEZ

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/10 ,  H01L21/02

Abstract: Gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. A dielectric cap is over the first vertical arrangement of nanowires. A second vertical arrangement of nanowires is above the substrate. Individual ones of the second vertical arrangement of nanowires are laterally staggered with individual ones of the first vertical arrangement of nanowires and the dielectric cap.

公开(公告)号：US20200286891A1

公开(公告)日：2020-09-10

申请号：US16294380

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Kiran CHIKKADI

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/308 ,  H01L23/00 ,  H01L23/528

Abstract: Self-aligned gate endcap (SAGE) architectures having local interconnects, and methods of fabricating SAGE architectures having local interconnects, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin, and a second gate structure over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between and in contact with the first and second gate structures. A local gate interconnect is between the gate plug and the gate endcap isolation structure, the local gate interconnect in contact with the first and second gate structures.

公开(公告)号：US20200286890A1

公开(公告)日：2020-09-10

申请号：US16294210

申请日：2019-03-06

Applicant: Intel Corporation

Inventor： Sairam SUBRAMANIAN ,  Walid M. HAFEZ

IPC: H01L27/092 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/768

Abstract: Self-aligned gate endcap (SAGE) architectures having gate contacts, and methods of fabricating SAGE architectures having gate contacts, are described. In an example, an integrated circuit structure includes a gate structure over a semiconductor fin. A gate endcap isolation structure is laterally adjacent to and in contact with the gate structure. A trench contact structure is over the semiconductor fin, where the gate endcap isolation structure is laterally adjacent to and in contact with the trench contact structure. A local gate-to-contact interconnect is electrically connecting the gate structure to the trench contact structure.

公开(公告)号：US20200251470A1

公开(公告)日：2020-08-06

申请号：US16846896

申请日：2020-04-13

Applicant: Intel Corporation

Inventor： Curtis TSAI ,  Chia-Hong JAN ,  Jeng-Ya David YEH ,  Joodong PARK ,  Walid M. HAFEZ

IPC: H01L27/092 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/49 ,  H01L27/088 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.

公开(公告)号：US20200066907A1

公开(公告)日：2020-02-27

申请号：US16317708

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Hong JAN ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Neville L. DIAS ,  Rahul RAMASWAMY ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.

公开(公告)号：US20190304971A1

公开(公告)日：2019-10-03

申请号：US15941647

申请日：2018-03-30

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Sridhar GOVINDARAJU ,  Mark LIU ,  Szuya S. LIAO ,  Chia-Hong JAN ,  Nick LINDERT ,  Christopher KENYON ,  Sairam SUBRAMANIAN

IPC: H01L27/088 ,  H01L23/528 ,  H01L29/06

Abstract: Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

公开(公告)号：US20170133461A1

公开(公告)日：2017-05-11

申请号：US15409065

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Walid M. HAFEZ ,  Chia-Hong JAN

IPC: H01L29/06 ,  H01L27/098

CPC classification number: H01L29/0649 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/404 ,  H01L29/66166 ,  H01L29/66803 ,  H01L29/66901 ,  H01L29/808 ,  H01L29/8605

Abstract: A dielectric and isolation lower fin material is described that is useful for fin-based electronics. In some examples, a dielectric layer is on first and second sidewalls of a lower fin. The dielectric layer has a first upper end portion laterally adjacent to the first sidewall of the lower fin and a second upper end portion laterally adjacent to the second sidewall of the lower fin. An isolation material is laterally adjacent to the dielectric layer directly on the first and second sidewalls of the lower fin and a gate electrode is over a top of and laterally adjacent to sidewalls of an upper fin. The gate electrode is over the first and second upper end portions of the dielectric layer and the isolation material.