公开(公告)号：US20160173055A1

公开(公告)日：2016-06-16

申请号：US14569981

申请日：2014-12-15

Applicant: INTEL CORPORATION

Inventor： Michael W. Leddige ,  Wei Jern Tan ,  Chee Kit Chew ,  Natasya Athirah Abdul Khalid ,  Howard L. Heck

IPC: H03H7/38 ,  H01P3/08

CPC classification number: H05K1/025 ,  H05K2201/0979

Abstract: Techniques for impedance matching are described herein. The techniques include an apparatus for impedance matching including a trace section having a load impedance. The trace section comprises characteristics generating an impedance match between a main channel impedance and the load impedance.

Abstract translation: 本文描述了用于阻抗匹配的技术。 这些技术包括用于阻抗匹配的装置，其包括具有负载阻抗的迹线部分。 迹线部分包括在主通道阻抗和负载阻抗之间产生阻抗匹配的特性。

公开(公告)号：US09632961B2

公开(公告)日：2017-04-25

申请号：US13844671

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Olufemi B. Oluwafemi ,  Stephen H. Hall ,  Jason A. Mix ,  Earl J. Wight ,  Chaitanya Sreerama ,  Michael W. Leddige ,  Paul G. Huray

IPC: G06F13/40

CPC classification number: G06F13/4004 ,  G06F13/4022

Abstract: Techniques for decoding encoded data are described herein. An example of a device in accordance with the present techniques includes a receiving signaling module coupled to a plurality of signal lines. The signaling module includes a receiver to receive a plurality of encoded line voltages or currents on the plurality of signal lines of a bus, wherein each one of the plurality of encoded line voltages corresponds to a weighted sum of data. The signaling module includes a comparator to determine the voltage level of each line at a unit interval and convert the voltage level to a digital value. The signaling module includes a lookup table correlating the digital value with a digital bit stream.

公开(公告)号：US08775991B2

公开(公告)日：2014-07-08

申请号：US13888627

申请日：2013-05-07

Applicant: Intel Corporation

Inventor： Michael W. Leddige ,  Kuljit Singh Bains ,  John Thomas Sprietsma

IPC: G06F17/50

CPC classification number: H01L23/49816 ,  G11C5/02 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10734 ,  H05K2203/1572 ,  Y02P70/611

Abstract: A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate. Other embodiments are also disclosed and claimed.

Abstract translation: 存储器模块具有连接阵列。 连接阵列以行和列排列，使得存在第一和第二外部列。 可以互换第一和第二外柱中的连接，以优化在基板上的双面模块放置。 还公开并要求保护其他实施例。

公开(公告)号：US09330039B2

公开(公告)日：2016-05-03

申请号：US13726748

申请日：2012-12-26

Applicant: INTEL CORPORATION

Inventor： Stephen H. Hall ,  Chaitanya Sreerama ,  Jason A. Mix ,  Michael W. Leddige ,  Jose A. Sanchez Sanchez ,  Olufemi B. Oluwafemi ,  Paul G. Huray ,  Maynard C. Falconer

IPC: G06F13/40

CPC classification number: G06F13/4022

Abstract: Techniques for encoding data are described herein. An example of a device in accordance with the present techniques includes a signaling module coupled to a plurality of digital inputs. The signaling module is to encode data received at the plurality of digital inputs to generate encoded data. Based on the encoded data, the signaling module can drive line voltages on a plurality of signal lines of a bus. Each one of the plurality of line voltages corresponds to a weighted sum of the data received at the plurality of digital inputs.

Abstract translation: 本文描述了用于编码数据的技术。 根据本技术的设备的示例包括耦合到多个数字输入的信令模块。 信令模块是对在多个数字输入端接收的数据进行编码，以生成编码数据。 基于编码数据，信令模块可以驱动总线的多个信号线上的线路电压。 多个线路电压中的每一个对应于在多个数字输入端接收的数据的加权和。

公开(公告)号：US10078612B2

公开(公告)日：2018-09-18

申请号：US14444616

申请日：2014-07-28

Applicant: INTEL CORPORATION

Inventor： Michael W. Leddige ,  Stephen H. Hall ,  Chaitanya Sreerama ,  Olufemi B. Oluwafemi ,  Antonio Zenteno Ramirez ,  Maynard C. Falconer

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/20

CPC classification number: G06F13/4221 ,  G06F13/20

Abstract: An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix.

公开(公告)号：US09910814B2

公开(公告)日：2018-03-06

申请号：US14658026

申请日：2015-03-13

Applicant: Intel Corporation

Inventor： Bryan L. Spry ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Rohit R. Verma ,  Lily P. Looi ,  Ronald W. Swartz ,  Michael W. Leddige ,  Vui Yong Liew

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/12

CPC classification number: G06F13/4221 ,  G06F13/122 ,  G06F13/4022 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express™ (PCIe™) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe™ format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips.

公开(公告)号：US20160026597A1

公开(公告)日：2016-01-28

申请号：US14444616

申请日：2014-07-28

Applicant: INTEL CORPORATION

Inventor： Michael W. Leddige ,  Stephen H. Hall ,  Chaitanya Sreerama ,  Olufemi B. Oluwafemi ,  Antonio Zenteno Ramirez ,  Maynard C. Falconer

IPC: G06F13/42 ,  G06F13/20

CPC classification number: G06F13/4221 ,  G06F13/20

Abstract: An apparatus is described herein. The apparatus includes a plurality of conductors, wherein at least one conductor is a common-mode conductor. The apparatus also includes an encoder to encode data to be transmitted on the plurality of conductors, wherein a data speed of the common-mode conductor is limited and a data speed of other conductors is maximized according to an encoding matrix.

Abstract translation: 这里描述了一种装置。 该装置包括多个导体，其中至少一个导体是共模导体。 该装置还包括编码器，用于编码要在多个导体上传输的数据，其中共模导体的数据速度受到限制，并且其他导体的数据速度根据编码矩阵最大化。