公开(公告)号：US11450672B2

公开(公告)日：2022-09-20

申请号：US16859600

申请日：2020-04-27

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Somnath Paul ,  Muhammad M. Khellah ,  Chen Koren

IPC: G11C17/16 ,  H01L27/11 ,  G11C11/418 ,  G11C11/419 ,  G11C11/412

Abstract: An ultra-deep compute Static Random Access Memory (SRAM) with high compute throughput and multi-directional data transfer capability is provided. Compute units are placed in both horizontal and vertical directions to achieve a symmetric layout while enabling communication between the compute units. An SRAM array supports simultaneous read and write to the left and right section of the same SRAM subarray by duplicating pre-decoding logic inside the SRAM array. This allows applications with non-overlapping read and write address spaces to have twice the bandwidth as compared to a baseline SRAM array.

公开(公告)号：US10423203B2

公开(公告)日：2019-09-24

申请号：US15392559

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Rafael Rios ,  Somnath Paul ,  Muhammad M. Khellah

IPC: G06F1/26 ,  H03K3/012 ,  G06F1/3293 ,  H03K3/356

Abstract: Embodiments include apparatuses, methods, and systems for a flip-flop circuit with low-leakage transistors. The flip-flop circuit may be coupled to a logic circuit of an integrated circuit to store data for the logic circuit when the logic circuit is in a sleep state. The flip-flop circuit may pass a data signal for the logic circuit along a signal path. A capacitor may be coupled between the signal path and ground to store a value of the data signal when the logic circuit is in the sleep state. A low-leakage transistor, such as an IGZO transistor, may be coupled between the capacitor and the signal path and may selectively turn on when the logic circuit transitions from the active state to the sleep state to store the value of the data signal in the capacitor. Other embodiments may be described and claimed.

公开(公告)号：US10418076B2

公开(公告)日：2019-09-17

申请号：US15706521

申请日：2017-09-15

Applicant: Intel Corporation

Inventor： Pascal A. Meinerzhagen ,  Stephen T. Kim ,  Anupama A. Thaploo ,  Muhammad M. Khellah

IPC: G11C5/14

Abstract: An apparatus is provided which comprises: a first power gate transistor coupled to an ungated power supply node and a gated power supply node, the first power gate transistor having a gate terminal controllable by a first logic; and a second power gate coupled to the ungated power supply node and the gated power supply node, the second power gate transistor having a gate terminal controllable by a second logic, wherein the first power gate transistor is larger than the second power gate transistor, and wherein the second logic is operable to: weakly turn on the second power gate, fully turn on the second power gate, turn off the second power gate, and connecting the second power gate as diode.

公开(公告)号：US20180294019A1

公开(公告)日：2018-10-11

申请号：US15485059

申请日：2017-04-11

Applicant: Intel Corporation

Inventor： Jaydeep P. Kulkarni ,  Muhammad M. Khellah

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/067 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/18 ,  G11C8/16 ,  G11C11/412 ,  G11C11/419 ,  G11C15/04

Abstract: Apparatuses, methods and storage media associated with single-ended sensing array design are disclosed herein. In embodiments, a memory device may include bitcell arrays, clipper circuitry, read merge circuitry, and a set dominant latch (SDL). The clipper circuitry may be coupled to a read port node of a first bitcell array of the bitcell arrays and a local bitline (LBL) node, the clipper circuitry to provide a voltage drop between the read port node and the LBL node. The read merge circuitry coupled to the clipper circuitry at the LBL node, the read merge circuitry to drive a value of a global bitline (GBL) node based on a value of the LBL node. The SDL coupled to the GBL node to sense the value of the GBL node. Other embodiments may be described and/or claimed.

公开(公告)号：US20180107922A1

公开(公告)日：2018-04-19

申请号：US15294666

申请日：2016-10-14

Applicant: Intel Corporation

Inventor： Somnath Paul ,  Charles Augustine ,  Muhammad M. Khellah

IPC: G06N3/08 ,  G06N99/00

Abstract: A processor or integrated circuit includes a memory to store weight values for a plurality neuromorphic states and a circuitry coupled to the memory. The circuitry is to detect an incoming data signal for a pre-synaptic neuromorphic state and initiate a time window for the pre-synaptic neuromorphic state in response to detecting the incoming data signal. The circuitry is further to, responsive to detecting an end of the time window: retrieve, from the memory, a weight value for a post-synaptic neuromorphic state for which an outgoing data signal is generated during the time window, the post-synaptic neuromorphic state being a fan-out connection of the pre-synaptic neuromorphic state; perform a causal update to the weight value, according to a learning function, to generate an updated weight value; and store the updated weight value back to the memory.

公开(公告)号：US20180107919A1

公开(公告)日：2018-04-19

申请号：US15370542

申请日：2016-12-06

Applicant: Intel Corporation

Inventor： Somnath Paul ,  Charles Augustine ,  Muhammad M. Khellah

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: Systems, apparatuses and methods may provide a hybrid compression scheme to store synaptic weights in neuromorphic cores. The hybrid compression scheme utilizes a run-length encoding (RLE) compression approach, a dictionary-based encode compression scheme, and a compressionless encoding scheme to store the weights for valid synaptic connections in a synaptic weight memory.

公开(公告)号：US20170322617A1

公开(公告)日：2017-11-09

申请号：US15409366

申请日：2017-01-18

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Muhammad M. Khellah ,  James W. Tschanz

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/172

Abstract: Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.

公开(公告)号：US20160173092A1

公开(公告)日：2016-06-16

申请号：US14569569

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Amit R. Trivedi ,  Jaydeep P. Kulkarni ,  Dinesh Somasekhar ,  Muhammad M. Khellah ,  Carlos Tokunaga ,  James W. Tschanz

IPC: H03K19/0175

CPC classification number: H03K19/017509

Abstract: Described is an apparatus which comprises: a first power supply node to provide a first power supply; a second power supply node to provide a second power supply; a driver to operate on the first power supply, the driver to generate an output; and a receiver to operate on the second power supply, the receiver to receive the output from the driver and to generate a level-shifted output such that the receiver is operable to steer current from the second power supply to the first power supply.

Abstract translation: 描述了一种装置，其包括：第一电源节点，用于提供第一电源; 第二电源节点，用于提供第二电源; 驱动器在第一电源上运行，驱动器产生输出; 以及接收器，用于在所述第二电源上操作，所述接收器接收来自所述驱动器的输出并产生电平移位输出，使得所述接收器可操作以将电流从所述第二电源转向所述第一电源。

公开(公告)号：US08824198B2

公开(公告)日：2014-09-02

申请号：US13906230

申请日：2013-05-30

Applicant: Intel Corporation

Inventor： Vivek K. De ,  DiaaEidin S. Khalil ,  Muhammad M. Khellah ,  Moty Mehalel ,  George Shchupak

IPC: G11C11/00 ,  G11C11/412

CPC classification number: G11C5/142 ,  G11C5/063 ,  G11C11/412 ,  G11C11/413

Abstract: A register file employing a shared supply structure to improve the minimum supply voltage.

Abstract translation: 采用共享供电结构的寄存器文件来提高最小电源电压。

公开(公告)号：US20240331761A1

公开(公告)日：2024-10-03

申请号：US18126680

申请日：2023-03-27

Applicant: Intel Corporation

Inventor： Charles Augustine ,  Amlan Ghosh ,  Seenivasan Subramaniam ,  Patrick Morrow ,  Muhammad M. Khellah ,  Feroze Merchant

IPC: G11C11/4096 ,  G11C11/4093 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4093 ,  G11C11/4094

Abstract: An apparatus includes a first write bit line (WBL), a first P-channel metal oxide semiconductor (PMOS) transistor including a source coupled to the WBL, a first inverter including an input coupled to a drain of the first PMOS transistor, and a second PMOS transistor including a source coupled to an output of the first inverter. The first PMOS transistor and the second PMOS transistor are disposed in at least one PMOS layer configured between a first metal layer and a second metal layer. The register file circuit further includes a first via connecting a gate of the first PMOS transistor and a gate of the second PMOS transistor in the at least one PMOS layer to the first metal layer.