-
公开(公告)号：US20240222347A1
公开(公告)日：2024-07-04
申请号：US18148338
申请日：2022-12-29
申请人： Intel Corporation
发明人： Sagar Suthram , Kuljit S. Bains , Wilfred Gomes , Don Douglas Josephson , Surhud V. Khare , Christopher Philip Mozak , Randy B. Osborne , Pushkar Ranade , Abhishek Anil Sharma
CPC分类号： H01L25/18 , H01L23/481 , H01L24/16 , H10B80/00 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541
摘要： In embodiments herein, an integrated circuit device includes a logic die with processor circuitry and a memory die coupled to the logic die. The memory die includes a first memory module comprising a first memory bank and first control circuitry, a second memory module comprising a second memory bank and second control circuitry, and a scribe line on a surface of the memory die between the first memory module and the second memory module. The first memory module is not electrically connected to the second memory module, and each memory module include through silicon vias (TSVs) to electrically connect a top side of the memory module and a bottom side of the memory module (e.g., for three-dimensional stacking in the integrated circuit device).
-
公开(公告)号：US20240211400A1
公开(公告)日：2024-06-27
申请号：US18069249
申请日：2022-12-21
申请人： Intel Corporation
IPC分类号： G06F12/0815
CPC分类号： G06F12/0815 , G06F2212/1024
摘要： In one embodiment, a semiconductor package comprises: a first die comprising: a plurality of cores; and memory circuitry comprising a memory controller and a memory side cache controller to maintain tag information and state information for a data array; and a second die coupled to the first die, the second die comprising the data array to cache data for at least one accelerator, the at least one accelerator remote from the first die. The memory side cache controller may be configured to control the data array. Other embodiments are described and claimed.
-
公开(公告)号：US10580107B2
公开(公告)日：2020-03-03
申请号：US15961526
申请日：2018-04-24
申请人： INTEL CORPORATION
IPC分类号： G06T1/20
摘要： A system for automatic hardware ZLW insertion for IPU image streams is described herein. The system includes a memory and a processor. The memory is to store imaging data. The processor is coupled to the memory. The processor is to receive an image stream request and determine a data transfer type. The processor is also to insert a zero length write (ZLW) instruction ahead of the image stream request in response to the image stream request beginning on a different page when compared to the current page in a page history. Additionally, the processor is to insert a ZLW instruction ahead of the image stream request in response to the image stream request crossing a page boundary.
-
公开(公告)号：US12057402B2
公开(公告)日：2024-08-06
申请号：US17025166
申请日：2020-09-18
申请人： Intel Corporation
发明人： Aleksandar Aleksov , Adel A. Elsherbini , Shawna M. Liff , Johanna M. Swan , Feras Eid , Randy B. Osborne , Van H. Le
IPC分类号： H01L23/538 , H01L23/49 , H01L25/065
CPC分类号： H01L23/5384 , H01L23/49 , H01L23/5385 , H01L23/5386 , H01L25/0657
摘要： Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include an interposer, including an organic dielectric material, and a microelectronic component coupled to the interposer by direct bonding.
-
公开(公告)号：US20220093517A1
公开(公告)日：2022-03-24
申请号：US17025166
申请日：2020-09-18
申请人： Intel Corporation
发明人： Aleksandar Aleksov , Adel A. Elsherbini , Shawna M. Liff , Johanna M. Swan , Feras Eid , Randy B. Osborne , Van H. Le
IPC分类号： H01L23/538 , H01L25/065 , H01L23/49
摘要： Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include an interposer, including an organic dielectric material, and a microelectronic component coupled to the interposer by direct bonding.
-
公开(公告)号：US20240339410A1
公开(公告)日：2024-10-10
申请号：US18746188
申请日：2024-06-18
申请人： Intel Corporation
发明人： Aleksandar Aleksov , Adel A. Elsherbini , Shawna M. Liff , Johanna M. Swan , Feras Eid , Randy B. Osborne , Van H. Le
IPC分类号： H01L23/538 , H01L23/49 , H01L25/065
CPC分类号： H01L23/5384 , H01L23/49 , H01L23/5385 , H01L23/5386 , H01L25/0657
摘要： Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, as well as related structures and techniques. For example, in some embodiments, a microelectronic assembly may include a first microelectronic component, including an organic dielectric material; a second microelectronic component coupled to the first microelectronic component by a direct bonding region, wherein the direct bonding region includes metal contacts and a dielectric material between adjacent ones of the metal contacts, and wherein the dielectric material includes an inorganic dielectric material; and a third microelectronic component coupled to the first microelectronic component by wire bonding or solder.
-
公开(公告)号：US20170140809A1
公开(公告)日：2017-05-18
申请号：US15351195
申请日：2016-11-14
申请人： Intel Corporation
IPC分类号： G11C11/4093 , G11C11/4096 , G11C11/4076
CPC分类号： G11C11/4093 , G06F13/1684 , G06F13/1689 , G11C11/4076 , G11C11/4096
摘要： Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US20180239605A1
公开(公告)日：2018-08-23
申请号：US15961526
申请日：2018-04-24
申请人： INTEL CORPORATION
CPC分类号： G06T1/20 , G06F9/30047 , G06T2200/28
摘要： A system for automatic hardware ZLW insertion for IPU image streams is described herein. The system includes a memory and a processor. The memory is to store imaging data. The processor is coupled to the memory. The processor is to receive an image stream request and determine a data transfer type. The processor is also to insert a zero length write (ZLW) instruction ahead of the image stream request in response to the image stream request beginning on a different page when compared to the current page in a page history. Additionally, the processor is to insert a ZLW instruction ahead of the image stream request in response to the image stream request crossing a page boundary.
-
公开(公告)号：US20180226118A1
公开(公告)日：2018-08-09
申请号：US15944755
申请日：2018-04-03
申请人： Intel Corporation
IPC分类号： G11C11/4093 , G11C11/4076 , G11C11/4096
CPC分类号： G11C11/4093 , G06F13/1684 , G06F13/1689 , G11C11/4076 , G11C11/4096
摘要： Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory with multiple ranks. Other embodiments are also disclosed and claimed.
-
公开(公告)号：US09983877B2
公开(公告)日：2018-05-29
申请号：US15280772
申请日：2016-09-29
申请人： INTEL CORPORATION
CPC分类号： G06F9/3802 , G06F9/3851 , G06T1/20 , G06T2200/28
摘要： A system for automatic hardware ZLW insertion for IPU image streams is described herein. The system includes a memory and a processor. The memory is to store imaging data. The processor is coupled to the memory. The processor is to receive an image stream request and determine a data transfer type. The processor is also to insert a zero length write (ZLW) instruction ahead of the image stream request in response to the image stream request beginning on a different page when compared to the current page in a page history. Additionally, the processor is to insert a ZLW instruction ahead of the image stream request in response to the image stream request crossing a page boundary.
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.017 秒)
