公开(公告)号：US11481352B2

公开(公告)日：2022-10-25

申请号：US17134293

申请日：2020-12-26

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Nobuyuki Suzuki ,  Anoop Mukker ,  Daniel Nemiroff ,  David W. Vogel

IPC: G06F13/42 ,  G06F1/24 ,  G06F1/08 ,  G06F1/3287 ,  G06F9/4401

Abstract: An example includes detecting receiving a bus turn-around (BTA) sequence after detecting a voltage level; sending a BTA acknowledgement in response to the BTA sequence; and sending a configuration command to a peripheral device after the interface is initialized based on the BTA acknowledgement.

公开(公告)号：US20210389371A1

公开(公告)日：2021-12-16

申请号：US17461364

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Vui Yong Liew ,  Zhenyu Zhu ,  Mikal C. Hunsaker ,  Wai Mun Ng

IPC: G01R31/317 ,  G01R31/3185 ,  G01R31/3193 ,  G06F13/16 ,  G06F13/42

Abstract: An apparatus comprises a first semiconductor chip comprising a first communication controller to receive first debug data from a second semiconductor chip; a memory to store the first debug data from the second semiconductor chip and second debug data of the first semiconductor chip; and a second communication controller to transmit the first debug data from the second semiconductor chip and the second debug data of the first semiconductor chip to an output port of the first semiconductor chip.

公开(公告)号：US11048659B2

公开(公告)日：2021-06-29

申请号：US16254266

申请日：2019-01-22

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Nobuyuki Suzuki ,  Anoop Mukker ,  Daniel Nemiroff ,  David W. Vogel

IPC: G06F13/42 ,  G06F1/24 ,  G06F1/08 ,  G06F1/3287 ,  G06F9/4401

Abstract: An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a reset sequence and an initialization of a link configuration register. The method also includes driving a high voltage signal to the clock lanes and the data lanes. The method further includes driving a bus turn-around (BTA) sequence on the data lanes. The method also includes detecting that the BTA is acknowledged by a host controller.

公开(公告)号：US11036409B2

公开(公告)日：2021-06-15

申请号：US15843545

申请日：2017-12-15

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Chai Huat Gan ,  Mikal Hunsaker

IPC: G06F3/06 ,  G06F12/02 ,  G06F13/42 ,  G06F13/16

Abstract: A first signal may be received from a memory device at a first interconnect terminal of a number of interconnect terminals via a serial communication interface that indicates the memory device includes a NAND type memory device. Whether a second signal that indicates the NAND type memory device is initialized has been received from the memory device at a second interconnect terminal of the number of interconnect terminals may be determined. An operation associated with the NAND type memory device may be performed at the second interconnect terminal and a third interconnect terminal in response to determining the second signal has been received from the memory device indicating the NAND type memory device is initialized.

公开(公告)号：US10719469B2

公开(公告)日：2020-07-21

申请号：US15445592

申请日：2017-02-28

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Mikal C Hunsaker ,  Christopher J. Lake ,  Kie Woon Lim

IPC: G06F13/38 ,  G06F13/364 ,  G06F13/42 ,  G06F13/40

Abstract: A method implemented by a system on a chip (SOC) system executing an enhance serial peripheral interconnect (eSPI) master. The method to receive an alert from an eSPI slave, send a get out of band message to the eSPI slave, and receive an out of band message from the eSPI slave including a connection or disconnection command. The method enabling the SOC to include an embedded multiplexor for managing the role of a universal serial bus (USB) Type-C connector.

公开(公告)号：US20190391949A1

公开(公告)日：2019-12-26

申请号：US16254266

申请日：2019-01-22

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Nobuyuki Suzuki ,  Anoop Mukker ,  Daniel Nemiroff ,  David W. Vogel

IPC: G06F13/42 ,  G06F1/08 ,  G06F1/24 ,  G06F1/3287 ,  G06F9/4401

Abstract: An example method for initializing an interface includes driving a low voltage signal on data lanes and clock lanes. The method further includes performing a reset sequence and an initialization of a link configuration register. The method also includes driving a high voltage signal to the clock lanes and the data lanes. The method further includes driving a bus turn-around (BTA) sequence on the data lanes. The method also includes detecting that the BTA is acknowledged by a host controller.

公开(公告)号：US20190155753A1

公开(公告)日：2019-05-23

申请号：US16258828

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Mikal Hunsaker ,  Chai Huat Gan

IPC: G06F12/14 ,  G06F21/64 ,  G06F21/79 ,  G06F21/60

Abstract: In one embodiment, an apparatus includes: an interface controller to receive a request from an external device coupled to the apparatus to access a flash memory coupled to the apparatus, the request comprising an access request to a replay protection monotonic counter (RPMC) of the flash memory; and a flash controller coupled to the interface controller. In turn, the flash controller includes: an atomic sequencer to arbitrate accesses to the RPMC by a plurality of components; and a mapper to map the access request to a selected counter of the RPMC associated with the external device. Other embodiments are described and claimed.

公开(公告)号：US20230161723A1

公开(公告)日：2023-05-25

申请号：US17531522

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Kishore Kasichainula ,  Satheesh Chellappan ,  Zhenyu Zhu

IPC: G06F13/38 ,  G06F13/42 ,  H02J7/00

CPC classification number: G06F13/382 ,  G06F13/4282 ,  H02J7/0047 ,  H02J7/00032 ,  G06F2213/0042

Abstract: Embodiments herein relate to an electronic device that includes a system-on-chip (SoC). The electronic device may further include a USB port to provide a first identification signal that is at a first voltage and that is related to a charging process between a USB device to which the USB port is coupled an the electronic device. The electronic device may further include a power delivery (PD) controller to: generate, based on the first identification signal, a second identification signal at a second voltage that is lower than the first voltage; and provide the second identification signal to the SoC. Other embodiments may be described and claimed.

公开(公告)号：US11568048B2

公开(公告)日：2023-01-31

申请号：US17131985

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Nivedita Aggarwal ,  Zhenyu Zhu ,  Michael Berger

IPC: G06F21/55 ,  G06F11/14 ,  G06F13/42 ,  G06F21/57 ,  H04L9/32 ,  G06F11/07 ,  G06F11/20 ,  H04L9/08

Abstract: An apparatus to facilitate descriptor resiliency in a computer system platform is disclosed. The apparatus comprises a non-volatile memory to store firmware for a computer system platform, wherein the firmware comprises a primary descriptor including access permission details for platform components and a secondary descriptor including a backup copy of the access permission details and a controller, coupled to the first non-volatile memory, including recovery hardware to detect a problem during a platform reset with the primary descriptor, recover the contents of the primary descriptor from the backup copy included in the secondary descriptor and store the contents of the backup copy to primary descriptor.

公开(公告)号：US11119704B2

公开(公告)日：2021-09-14

申请号：US16367608

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Zhenyu Zhu ,  Mikal Hunsaker ,  Karthi R. Vadivelu ,  Rahul Bhatt ,  Kenneth P. Foust ,  Rajesh Bhaskar ,  Amit Kumar Srivastava

IPC: G06F3/06 ,  G06F13/38 ,  G06F9/54

Abstract: In one embodiment, a flash sharing controller is to enable a plurality of components of a platform to share a flash memory. The flash sharing controller may include: a flash sharing class layer including a configuration controller to configure the plurality of components to be flash master devices and configure a flash sharing slave device for the flash memory; and a physical layer coupled to the flash sharing class layer to communicate with the plurality of components via a bus. Other embodiments are described and claimed.