Method and apparatus for EUV mask having diffusion barrier

    公开(公告)号:US08940463B2

    公开(公告)日:2015-01-27

    申请号:US13827969

    申请日:2013-03-14

    Inventor: Wim Y. Deweerd

    CPC classification number: G03F1/52 G03F1/22 G03F1/24

    Abstract: A photomask is provide. The photomask includes a substrate having a multi-layer stack disposed over the substrate. The multilayer stack has alternating first second and third layers disposed over each other, wherein the first, second and third layers are composed of first, second and third materials, respectively, and wherein at least the second layer is formed through an atomic layer deposition process. A capping layer is disposed over the multilayer stack; and an absorber layer disposed over the capping layer. A method for evaluating materials, unit processes, and process sequences for manufacturing a photomask is also provided.

    Method and apparatus for EUV mask having diffusion barrier
    2.
    发明授权
    Method and apparatus for EUV mask having diffusion barrier 有权
    具有扩散阻挡层的EUV掩模的方法和装置

    公开(公告)号:US08936889B2

    公开(公告)日:2015-01-20

    申请号:US13804011

    申请日:2013-03-14

    Inventor: Wim Y. Deweerd

    CPC classification number: G03F1/52 G03F1/22 G03F1/24

    Abstract: A photomask is provide. The photomask includes a substrate having a multi-layer stack disposed over the substrate. The multilayer stack has alternating first second and third layers disposed over each other, wherein the first, second and third layers are composed of first, second and third materials, respectively, and wherein at least the second layer is formed through an atomic layer deposition process. A capping layer is disposed over the multilayer stack; and an absorber layer disposed over the capping layer. A method for evaluating materials, unit processes, and process sequences for manufacturing a photomask is also provided.

    Abstract translation: 提供光掩模。 光掩模包括具有设置在衬底上的多层堆叠的衬底。 所述多层叠层具有彼此交替设置的交替的第一第二和第三层,其中所述第一层,第二层和第三层分别由第一,第二和第三材料构成,并且其中至少所述第二层通过原子层沉积工艺形成 。 覆盖层设置在多层叠层上; 以及设置在所述封盖层上的吸收层。 还提供了用于评估用于制造光掩模的材料,单元工艺和工艺顺序的方法。

    Method and Apparatus For EUV Mask Having Diffusion Barrier
    3.
    发明申请
    Method and Apparatus For EUV Mask Having Diffusion Barrier 审中-公开
    具有扩散屏障的EUV掩模的方法和装置

    公开(公告)号:US20130196257A1

    公开(公告)日:2013-08-01

    申请号:US13804011

    申请日:2013-03-14

    Inventor: Wim Y. Deweerd

    CPC classification number: G03F1/52 G03F1/22 G03F1/24

    Abstract: A photomask is provide. The photomask includes a substrate having a multi-layer stack disposed over the substrate. The multilayer stack has alternating first second and third layers disposed over each other, wherein the first, second and third layers are composed of first, second and third materials, respectively, and wherein at least the second layer is formed through an atomic layer deposition process. A capping layer is disposed over the multilayer stack; and an absorber layer disposed over the capping layer. A method for evaluating materials, unit processes, and process sequences for manufacturing a photomask is also provided.

    Abstract translation: 提供光掩模。 光掩模包括具有设置在衬底上的多层堆叠的衬底。 所述多层叠层具有彼此交替设置的交替的第一第二和第三层,其中所述第一层,第二层和第三层分别由第一,第二和第三材料构成,并且其中至少所述第二层通过原子层沉积工艺形成 。 覆盖层设置在多层叠层上; 以及设置在所述封盖层上的吸收层。 还提供了用于评估用于制造光掩模的材料,单元工艺和工艺顺序的方法。

    Blocking layers for leakage current reduction in DRAM devices

    公开(公告)号:US08569818B2

    公开(公告)日:2013-10-29

    申请号:US13658065

    申请日:2012-10-23

    CPC classification number: H01L28/60 H01L27/10852 H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    Blocking Layers for Leakage Current Reduction in DRAM Devices
    7.
    发明申请
    Blocking Layers for Leakage Current Reduction in DRAM Devices 有权
    阻止DRAM器件泄漏电流降低的层

    公开(公告)号:US20130113079A1

    公开(公告)日:2013-05-09

    申请号:US13658065

    申请日:2012-10-23

    CPC classification number: H01L28/60 H01L27/10852 H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

    Manufacturable high-k DRAM MIM capacitor structure

    公开(公告)号:US08679939B2

    公开(公告)日:2014-03-25

    申请号:US13737467

    申请日:2013-01-09

    CPC classification number: H01L28/56 H01L27/10852 H01L28/60 H01L28/90

    Abstract: A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin ( 3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.

    Blocking layers for leakage current reduction in DRAM devices
    9.
    发明授权
    Blocking layers for leakage current reduction in DRAM devices 有权
    阻塞层用于DRAM器件的漏电流降低

    公开(公告)号:US08574999B2

    公开(公告)日:2013-11-05

    申请号:US13738865

    申请日:2013-01-10

    CPC classification number: H01L28/60 H01L27/10852 H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

    Leakage reduction in DRAM MIM capacitors
    10.
    发明申请
    Leakage reduction in DRAM MIM capacitors 审中-公开
    DRAM MIM电容器的漏电减少

    公开(公告)号:US20140077336A1

    公开(公告)日:2014-03-20

    申请号:US13737125

    申请日:2013-01-09

    CPC classification number: H01L29/92 H01L27/10852 H01L28/40

    Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high-k phase of a subsequently deposited dielectric layer. The high-k dielectric layer includes a doped material that can be crystallized after a subsequent annealing treatment. An amorphous blocking is formed on the dielectric layer. The thickness of the blocking layer is chosen such that the blocking layer remains amorphous after a subsequent annealing treatment. A second electrode layer compatible with the blocking layer is formed on the blocking layer.

    Abstract translation: 用于形成具有低漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 在电介质层上形成无定形阻挡层。 选择阻挡层的厚度使得在随后的退火处理之后阻挡层保持无定形。 在阻挡层上形成与阻挡层相容的第二电极层。

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