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公开(公告)号：US20250005412A1
公开(公告)日：2025-01-02
申请号：US18212947
申请日：2023-06-22
Applicant: International Business Machines Corporation
Inventor： Youngseok Kim , Xuan Wei , Isaac Lauer , Abhinav Kandala
IPC: G06N10/40
Abstract: A method, system and computer program product for calibrating a quantum operation. Layers of two qubit gates that operate in parallel are defined. A gate length for each two qubit gate in a layer of the defined layers is calibrated to correspond to the same gate length, such as the gate length of the two qubit gate in that layer with the slowest operation speed. A portion of the quantum operation is performed by the two qubit gates in the layer with the calibrated gate length. In this manner, two qubit gates that operate in parallel are effectively calibrated in a manner that results in better gate fidelities, fewer frequency collisions and fewer undesirable transitions.
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公开(公告)号：US11695483B2
公开(公告)日：2023-07-04
申请号：US16795149
申请日：2020-02-19
Applicant: International Business Machines Corporation
Inventor： Isaac Lauer , Neereja Sundaresan
Abstract: Systems, computer-implemented methods, and/or computer program products that can facilitate target qubit decoupling in an echoed cross-resonance gate are provided. According to an embodiment, a computer-implemented method can comprise receiving, by a system operatively coupled to a processor, both a cross-resonance pulse and a decoupling pulse at a target qubit. The cross-resonance pulse propagates to the target qubit via a control qubit. The computer-implemented method can further comprise receiving, by the system, a state inversion pulse at the control qubit. The computer-implemented method can further comprise receiving, by the system, both a phase-inverted cross-resonance pulse and a phase-inverted decoupling pulse at the target qubit. The phase-inverted cross-resonance pulse propagates to the target qubit via the control qubit.
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公开(公告)号：US11678591B2
公开(公告)日：2023-06-13
申请号：US17037109
申请日：2020-09-29
Applicant: International Business Machines Corporation
Inventor： Isaac Lauer , Karthik Balakrishnan , Jeffrey Sleight , David James Frank
CPC classification number: H01L39/025 , G06N10/00 , H01L39/04 , H01L39/223 , H01L39/2493
Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity.
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公开(公告)号：US20220383169A1
公开(公告)日：2022-12-01
申请号：US17324624
申请日：2021-05-19
Applicant: International Business Machines Corporation
Inventor： Abhinav Kandala , David C. Mckay , Isaac Lauer , Easwar Magesan
IPC: G06N10/00 , H03K19/195 , G06F9/448 , G06F9/38
Abstract: Systems, devices, computer-implemented methods, and/or computer program products that facilitate dynamic control of ZZ interactions for quantum computing devices. In one example, a quantum device can comprise a biasing component that is operatively coupled to first and second qubits via respective first and second drive lines. The biasing component can facilitate dynamic control of ZZ interactions between the first and second qubits using continuous wave (CW) tones applied via the respective first and second drive lines.
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公开(公告)号：US20220123449A1
公开(公告)日：2022-04-21
申请号：US17076107
申请日：2020-10-21
Applicant: International Business Machines Corporation
Inventor： Isaac Lauer , William Francis Landers , Srikanth Srinivasan , Neereja Sundaresan
Abstract: Techniques regarding an embedded microstrip transmission line implemented in one more superconducting microwave electronic devices are provided. For example, one or more embodiments described herein can comprise an apparatus, which can include a superconducting material layer positioned on a raised portion of a dielectric substrate. The raised portion can extend from a surface of the dielectric substrate. The apparatus can also comprise a dielectric film that covers at least a portion of the superconducting material layer and the raised portion of the dielectric substrate.
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Patent Agency Ranking
公开(公告)号：US20220102613A1
公开(公告)日：2022-03-31
申请号：US17037191
申请日：2020-09-29
Applicant: International Business Machines Corporation
Inventor： Isaac Lauer , Karthik Balakrishnan , Jeffrey Sleight , David James Frank
Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity.
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公开(公告)号：US20220102612A1
公开(公告)日：2022-03-31
申请号：US17037109
申请日：2020-09-29
Applicant: International Business Machines Corporation
Inventor： Isaac Lauer , Karthik Balakrishnan , Jeffrey Sleight , David James Frank
Abstract: Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity.
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8.发明授权公开(公告)号：US10680061B2
公开(公告)日：2020-06-09
申请号：US16375218
申请日：2019-04-04
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Xin Miao
IPC: H01L27/12 , H01L29/06 , H01L29/66 , H01L29/08 , H01L29/423 , H01L29/10 , H01L21/84 , H01L29/417 , H01L29/78
Abstract: Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Spacers are formed, with at least one top pair of spacers being positioned above an uppermost channel layer. The top pair of spacers each has a curved lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack.
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9.发明申请公开(公告)号：US20200091289A1
公开(公告)日：2020-03-19
申请号：US16690338
申请日：2019-11-21
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Xin Miao
IPC: H01L29/06 , H01L29/78 , H01L29/66 , H01L29/417 , H01L29/10 , H01L27/12 , H01L29/423 , H01L29/08 , H01L21/84
Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
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10.发明授权公开(公告)号：US10573714B2
公开(公告)日：2020-02-25
申请号：US16100425
申请日：2018-08-10
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Josephine B. Chang , Michael A. Guillorn , Isaac Lauer , Xin Miao
IPC: H01L27/12 , H01L29/06 , H01L29/66 , H01L29/08 , H01L29/423 , H01L29/10 , H01L29/417 , H01L29/78
Abstract: Field effect transistors and methods of forming the same include forming a stack of nanosheets of alternating layers of channel material and sacrificial material. A layer of sacrificial material forms a top layer of the stack. A dummy gate is formed over the stack. Stack material outside of a region covered by the dummy gate is removed. The sacrificial material is etched to form recesses in the sacrificial material layers. Spacers are formed in the recesses in the sacrificial material layers. At least one pair of spacers is formed in recesses above an uppermost layer of channel material. The dummy gates are etched away. The top layer of sacrificial material protects an uppermost layer of channel material from damage from the anisotropic etch. The sacrificial material is etched away to expose the layers of channel material. A gate stack is formed over, around, and between the layers of channel material.
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