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公开(公告)号：US11526433B2
公开(公告)日：2022-12-13
申请号：US16816504
申请日：2020-03-12
Applicant: International Business Machines Corporation
Inventor： Archana Ravindar , Saravanan Sethuraman , Vaidyanathan Srinivasan
Abstract: A method, a computer program product, and a system for allocating a variable into storage class memory during compilation of a program. The method includes selecting a variable recorded in a symbol table during compilation and computing a variable size of the variable by analyzing attributes related to the variable. The method further includes computing additional attributes relating to the variable. The method also includes computing a control flow graph and analyzing the control flow graph and the additional attributes to determine an allocation location for the variable. The method further includes allocating the variable into a storage class memory based on the analysis performed.
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公开(公告)号：US10606713B2
公开(公告)日：2020-03-31
申请号：US15860875
申请日：2018-01-03
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Kyu-hyoun Kim , Warren E. Maule , Kevin M. McIlvain , Saravanan Sethuraman
Abstract: A technique relates to operating a memory controller. A feedback mode is initiated such that an identified memory device of first memory devices includes an identified bit lane on a data bus to be utilized for testing. A process includes sending commands on the 1-N bit lanes of the command address bus to a buffer and duplicating commands designated for a selected one of the 1-N bit lanes. The process includes sending the duplicated commands on the identified bit lane in route to the buffer, and receiving a result of a parity check for the commands sent on the 1-N bit lanes, such that when the result is a pass the process ends. When the result is a fail, a duplicated parity check is performed using duplicated commands on the identified bit lane in place of the selected one. When the duplicated parity check passes, the selected one is bad.
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公开(公告)号：US10534545B2
公开(公告)日：2020-01-14
申请号：US15847954
申请日：2017-12-20
Applicant: International Business Machines Corporation
Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary , John B. DeForge , Warren E. Maule , Kirk D. Peterson , Sridhar H. Rangarajan , Saravanan Sethuraman
Abstract: An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.
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公开(公告)号：US10394618B2
公开(公告)日：2019-08-27
申请号：US15650204
申请日：2017-07-14
Applicant: International Business Machines Corporation
Inventor： Briana E. Foxworth , Saravanan Sethuraman , Kevin M. Mcilvain , Lucas W. Mulkey , Adam J. McPadden
IPC: G06F9/50 , G05D23/19 , G06F1/3234
Abstract: Embodiments of the present disclosure relate to managing volatile and non-volatile memory. A set of volatile memory sensor data may be obtained. A set of non-volatile memory sensor data may be obtained. The set of volatile memory sensor data and the set of non-volatile memory sensor data may be analyzed. A memory condition may be determined to exist based on the analysis. In response to determining that the memory condition exists, one or more memory actions may be issued.
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公开(公告)号：US20190243714A1
公开(公告)日：2019-08-08
申请号：US16392740
申请日：2019-04-24
Applicant: International Business Machines Corporation
Inventor： Briana E. Foxworth , Saravanan Sethuraman , Lucas W. Mulkey , Adam J. McPadden , Kevin M. Mcilvain
CPC classification number: G06F11/1441 , G06F3/0601 , G06F11/1456 , G06F13/4068 , G11C5/148 , G11C7/20 , G11C14/0018
Abstract: An NVDIMM requests an authentication object in response to a detected command to initiate a save operation to copy first memory data located in volatile memory on the NVDIMM to non-volatile memory located on the NVDIMM. The NVDIMM determines based on the authentication object that authentication has failed. The NVDIMM implements, in response to determining that authentication has failed, a security measure to prevent recovery of the first memory data.
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Patent Agency Ranking
公开(公告)号：US20190187915A1
公开(公告)日：2019-06-20
申请号：US15847954
申请日：2017-12-20
Applicant: International Business Machines Corporation
Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary , John B. DeForge , Warren E. Maule , Kirk D. Peterson , Sridhar H. Rangarajan , Saravanan Sethuraman
Abstract: An aspect includes receiving a request to write data to a memory that includes a stack of memory devices, each of the memory devices communicatively coupled to at least one other of the memory devices in the stack via a through silicon via (TSV). The write request is received by a hypervisor from an application executing on a virtual machine managed by the hypervisor. In response to receiving the request a latency requirement of accesses to the write data is determined. A physical location on a memory device in the stack of memory devices is assigned to the write data based at least in part on the latency requirement and a position of the memory device in the stack of memory devices. A write command that includes the physical location and the write data is sent to a memory controller.
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公开(公告)号：US10126968B2
公开(公告)日：2018-11-13
申请号：US14863590
申请日：2015-09-24
Applicant: International Business Machines Corporation
Inventor： John S. Bialas, Jr. , Stephen P. Glancy , Saravanan Sethuraman , Jacob D. Sloat
IPC: G06F3/06 , G06F12/0802
Abstract: In an example, a system includes a memory controller that includes a plurality of memory components. The system also includes a memory controller configured to receive a plurality of memory settings to be applied to the plurality of memory components. The memory controller is configured to, based on the received memory settings, transmit a first command to the plurality of memory components, the first command causing each memory component of the plurality of memory components to be configured to a first memory setting. The memory controller is configured to, based on the received memory settings, transmit a second command to a subset of the plurality of memory components after transmitting the first command, the second command causing each memory component of the subset to be configured to a second memory setting.
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公开(公告)号：US10069829B1
公开(公告)日：2018-09-04
申请号：US15718439
申请日：2017-09-28
Applicant: International Business Machines Corporation
Inventor： Saritha Arunkumar , Diyanesh B. Chinnakkonda Vidyapoornachary , Douglas J. Cowie , Saravanan Sethuraman
Abstract: In authentication in global attestation, a server receives a request for access to a location based service. The server establishes a connection with a first device and with a second device, wherein the devices are connected by a location bounded network. The server sends a key order information to the first device and a first plurality of keys to the second device. The server receives a second plurality of keys from the first device, wherein the second plurality of keys is an ordered set of keys compiled using the key order information and the first plurality of keys. The server determines that the second plurality of keys received from the first device matches an expected plurality of keys. The server outputs, to the location based service, a notification indicating a result of the determining that the second plurality of keys matches the expected plurality of keys.
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公开(公告)号：US10025508B2
公开(公告)日：2018-07-17
申请号：US14957180
申请日：2015-12-02
Applicant: International Business Machines Corporation
Inventor： Diyanesh B. Chinnakkonda Vidyapoornachary , Kyu-hyoun Kim , Saravanan Sethuraman , Gary A. Tressler
Abstract: An endurance parameter value of a non-volatile memory included in a non-volatile dual in-line memory module (NVDIMM) can be monitored and compared against a warning threshold value. In response to the endurance parameter exceeding the warning threshold value, a system alert can be generated, within a host system of the NVDIMM, to inform a system user that the NVDIMM is approaching its end-of-life. If the endurance parameter exceeds a replacement threshold value greater than the warning threshold value, an upgrade process can be initiated. The upgrade process can include copying data from the first non-volatile memory to a volatile memory of the NVDIMM and copying, in response to the first non-volatile memory being replaced with a second non-volatile memory, the data from the volatile memory to the second non-volatile memory.
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公开(公告)号：US09792209B2
公开(公告)日：2017-10-17
申请号：US14573970
申请日：2014-12-17
Applicant: International Business Machines Corporation
Inventor： Edgar R. Cordero , David M. Daly , Robert K. Montoye , Saravanan Sethuraman , Diyanesh B. Chinnakkonda Vidyapoornachary
IPC: G06F13/40 , G06F12/08 , G06F12/0811 , G06F13/16 , G06F9/455 , G06F9/50 , G06F12/0831 , G06F12/00 , G06F3/00
CPC classification number: G06F12/0811 , G06F3/00 , G06F9/45558 , G06F9/50 , G06F12/0833 , G06F13/1673 , G06F13/4045 , G06F2009/45583 , G06F2212/1016 , G06F2212/283 , G06F2212/62
Abstract: Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.
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