公开(公告)号：US10825716B2

公开(公告)日：2020-11-03

申请号：US16192277

申请日：2018-11-15

Applicant: Infineon Technologies AG

Inventor： Andreas Moser ,  Matteo Dainese ,  Matthias Kuenle ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L21/78 ,  H01L21/762 ,  H01L21/324 ,  H01L21/683 ,  H01L23/00 ,  H01L29/73 ,  H01L29/739

Abstract: An embodiment of a method for manufacturing a semiconductor device includes: providing a monocrystalline semiconductor substrate having a first side; forming a plurality of recess structures in the semiconductor substrate at the first side; filling the recess structures with a dielectric material to form dielectric islands in the recess structures; forming a semiconductor layer on the first side of the semiconductor substrate to cover the dielectric islands; and subjecting the semiconductor layer to heat treatment and recrystallizing the semiconductor layer to form a recrystallized semiconductor layer, so that a crystal structure of the recrystallized semiconductor layer adapts to a crystal structure of the semiconductor substrate, and so that the semiconductor substrate and the semiconductor layer together form a compound wafer with the dielectric islands at least partially buried in the semiconductor material of the compound wafer.

公开(公告)号：US10410911B2

公开(公告)日：2019-09-10

申请号：US15833781

申请日：2017-12-06

Applicant: Infineon Technologies AG

Inventor： Carsten Schaeffer ,  Andreas Moser ,  Matthias Kuenle ,  Matteo Dainese ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/739 ,  H01L21/8234 ,  H01L27/12 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.

公开(公告)号：US20160126149A1

公开(公告)日：2016-05-05

申请号：US14527811

申请日：2014-10-30

Applicant: Infineon Technologies AG

Inventor： Rudolf Zelsacher ,  Peter Irsigler ,  Erich Griebl ,  Manfred Pirker ,  Andreas Moser

IPC: H01L21/66 ,  H01L21/02 ,  H01L21/768 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L22/14 ,  H01L21/28158 ,  H01L22/34 ,  H01L29/66568 ,  H01L29/94

Abstract: According to various embodiments, a method for processing a substrate may include: forming a dielectric layer over the substrate, the dielectric layer may include a plurality of test regions; forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions; simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions from each other.

Abstract translation: 根据各种实施例，用于处理衬底的方法可以包括：在衬底上形成电介质层，电介质层可以包括多个测试区域; 在所述电介质层上形成导电层以接触所述多个测试区域中的介电层; 同时对多个测试区域中的电介质层进行电学检查，其中与多个测试区域中的电介质层接触的导电层的部分通过导电材料彼此导电连接; 以及将所述导电层分离成所述多个测试区域中与所述电介质层接触的所述导电层的部分。

公开(公告)号：US20190148217A1

公开(公告)日：2019-05-16

申请号：US16192277

申请日：2018-11-15

Applicant: Infineon Technologies AG

Inventor： Andreas Moser ,  Matteo Dainese ,  Matthias Kuenle ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L21/324 ,  H01L21/02 ,  H01L21/78

Abstract: An embodiment of a method for manufacturing a semiconductor device includes: providing a monocrystalline semiconductor substrate having a first side; forming a plurality of recess structures in the semiconductor substrate at the first side; filling the recess structures with a dielectric material to form dielectric islands in the recess structures; forming a semiconductor layer on the first side of the semiconductor substrate to cover the dielectric islands; and subjecting the semiconductor layer to heat treatment and recrystallizing the semiconductor layer to form a recrystallized semiconductor layer, so that a crystal structure of the recrystallized semiconductor layer adapts to a crystal structure of the semiconductor substrate, and so that the semiconductor substrate and the semiconductor layer together form a compound wafer with the dielectric islands at least partially buried in the semiconductor material of the compound wafer.

公开(公告)号：US09406572B2

公开(公告)日：2016-08-02

申请号：US14527811

申请日：2014-10-30

Applicant: Infineon Technologies AG

Inventor： Rudolf Zelsacher ,  Peter Irsigler ,  Erich Griebl ,  Manfred Pirker ,  Andreas Moser

IPC: H01L21/66 ,  H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L22/14 ,  H01L21/28158 ,  H01L22/34 ,  H01L29/66568 ,  H01L29/94

Abstract: According to various embodiments, a method for processing a substrate may include: forming a dielectric layer over the substrate, the dielectric layer may include a plurality of test regions; forming an electrically conductive layer over the dielectric layer to contact the dielectric layer in the plurality of test regions; simultaneously electrically examining the dielectric layer in the plurality of test regions, wherein portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions are electrically conductively connected with each other by an electrically conductive material; and separating the electrically conductive layer into portions of the electrically conductive layer contacting the dielectric layer in the plurality of test regions from each other.

Abstract translation: 根据各种实施例，用于处理衬底的方法可以包括：在衬底上形成电介质层，电介质层可以包括多个测试区域; 在所述电介质层上形成导电层以接触所述多个测试区域中的介电层; 同时对多个测试区域中的电介质层进行电学检查，其中与多个测试区域中的电介质层接触的导电层的部分通过导电材料彼此导电连接; 以及将所述导电层分离成所述多个测试区域中与所述电介质层接触的所述导电层的部分。

公开(公告)号：US09224806B2

公开(公告)日：2015-12-29

申请号：US13961155

申请日：2013-08-07

Applicant: Infineon Technologies AG

Inventor： Stephan Voss ,  Alexander Breymesser ,  Hans-Joachim Schulze ,  Erich Griebl ,  Oliver Haeberlen ,  Andreas Moser

IPC: H01L29/06 ,  H01L21/761

CPC classification number: H01L29/063 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor body and an edge termination structure. The edge termination structure comprises a first oxide layer, a second oxide layer, a semiconductor mesa region between the first oxide layer and the second oxide layer, and a doped field region comprising a first section in the semiconductor mesa region, and a second section in a region below the semiconductor mesa region. The second section overlaps the first and the second oxide layers in the region below the semiconductor mesa region.

Abstract translation: 半导体器件包括半导体本体和边缘端接结构。 边缘终端结构包括第一氧化物层，第二氧化物层，第一氧化物层和第二氧化物层之间的半导体台面区域，以及包括半导体台面区域中的第一部分的掺杂场区域，以及第二部分 半导体台面区域以下的区域。 第二部分与半导体台面区域下方的区域中的第一和第二氧化物层重叠。

公开(公告)号：US11515264B2

公开(公告)日：2022-11-29

申请号：US16421707

申请日：2019-05-24

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Alexander Breymesser ,  Erich Griebl ,  Michael Knabl ,  Matthias Kuenle ,  Andreas Moser ,  Roland Rupp ,  Hans-Joachim Schulze ,  Sokratis Sgouridis ,  Stephan Voss

IPC: H01L23/00 ,  H01L23/16

Abstract: A method for processing a semiconductor wafer is proposed. The method may include reducing a thickness of the semiconductor wafer. A carrier structure is placed on a first side of the semiconductor wafer, e.g. before or after reducing the thickness of the semiconductor wafer. The method further includes providing a support structure on a second side of the semiconductor wafer opposite to the first side, e.g. after reducing the thickness of the semiconductor wafer. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.

公开(公告)号：US20220359428A1

公开(公告)日：2022-11-10

申请号：US17869114

申请日：2022-07-20

Applicant: Infineon Technologies AG

Inventor： Francisco Javier Santos Rodriguez ,  Alexander Breymesser ,  Erich Griebl ,  Michael Knabl ,  Matthias Kuenle ,  Andreas Moser ,  Roland Rupp ,  Hans-Joachim Schulze ,  Sokratis Sgouridis ,  Stephan Voss

IPC: H01L23/00 ,  H01L23/16

Abstract: A method for processing a semiconductor wafer is proposed. The method may include: reducing a thickness of the semiconductor wafer; before or after reducing the thickness of the semiconductor wafer, placing a carrier structure at a first side of the semiconductor wafer; and after reducing the thickness of the semiconductor wafer, providing a support structure at a second side of the semiconductor wafer opposite to the first side. Methods for welding a support structure onto a semiconductor wafer are proposed. Further, semiconductor composite structures with support structures welded onto a semiconductor wafer are proposed.

公开(公告)号：US20180166324A1

公开(公告)日：2018-06-14

申请号：US15833781

申请日：2017-12-06

Applicant: Infineon Technologies AG

Inventor： Carsten Schaeffer ,  Andreas Moser ,  Matthias Kuenle ,  Matteo Dainese ,  Roland Rupp ,  Hans-Joachim Schulze

IPC: H01L21/762 ,  H01L21/3065 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L21/76248 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/02647 ,  H01L21/02667 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/3083 ,  H01L21/762 ,  H01L21/823481 ,  H01L21/823487 ,  H01L21/84 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/06 ,  H01L29/0649 ,  H01L29/08 ,  H01L29/0804 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/10 ,  H01L29/1095 ,  H01L29/66 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7812 ,  H01L29/7813

Abstract: A method of fabricating a semiconductor device includes forming a buried insulation region within a substrate by processing the substrate using etching and deposition processes. A semiconductor layer is formed over the buried insulation region at a first side of the substrate. Device regions are formed in the semiconductor layer. The substrate is thinned from a second side of the substrate to expose the buried insulation region. The buried insulation region is selectively removed to expose a bottom surface of the substrate. A conductive region is formed under the bottom surface of the substrate.

公开(公告)号：US20150041946A1

公开(公告)日：2015-02-12

申请号：US13961155

申请日：2013-08-07

Applicant: Infineon Technologies AG

Inventor： Stephan Voss ,  Alexander Breymesser ,  Hans-Joachim Schulze ,  Erich Griebl ,  Oliver Haeberlen ,  Andreas Moser

IPC: H01L29/06 ,  H01L21/761

CPC classification number: H01L29/063 ,  H01L21/761 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/66348 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor body and an edge termination structure. The edge termination structure comprises a first oxide layer, a second oxide layer, a semiconductor mesa region between the first oxide layer and the second oxide layer, and a doped field region comprising a first section in the semiconductor mesa region, and a second section in a region below the semiconductor mesa region. The second section overlaps the first and the second oxide layers in the region below the semiconductor mesa region.

Abstract translation: 半导体器件包括半导体本体和边缘端接结构。 边缘终端结构包括第一氧化物层，第二氧化物层，第一氧化物层和第二氧化物层之间的半导体台面区域，以及包括半导体台面区域中的第一部分的掺杂场区域，以及第二部分 半导体台面区域以下的区域。 第二部分与半导体台面区域下方的区域中的第一和第二氧化物层重叠。