公开(公告)号：US20230290773A1

公开(公告)日：2023-09-14

申请号：US17692509

申请日：2022-03-11

Applicant: Infineon Technologies AG

Inventor： Dethard PETERS ,  Guang ZENG

IPC: H01L27/02 ,  H01L27/06 ,  H01L29/16

CPC classification number: H01L27/0288 ,  H01L27/0629 ,  H01L29/1608

Abstract: An apparatus includes a junction termination edge, a unipolar power transistor, and an RC snubber. The RC snubber has a capacitor between a poly silicon structure and a semiconductor substrate, and part of the junction termination edge. The capacitor has a p-n junction. The RC snubber has a poly silicon resistor between a source of the unipolar power transistor and a first layer forming the capacitor. The unipolar transistor and the RC snubber are coupled in parallel. The RC snubber and the unipolar power transistor are formed monolithically on the semiconductor substrate.

公开(公告)号：US20250089323A1

公开(公告)日：2025-03-13

申请号：US18827272

申请日：2024-09-06

Applicant: Infineon Technologies AG

Inventor： Thomas AICHINGER ,  Dethard PETERS ,  Michael HELL ,  Andreas HÜRNER

IPC: H01L29/16 ,  H01L29/43 ,  H01L29/51 ,  H01L29/78

Abstract: A power semiconductor device is proposed. The vertical power semiconductor device includes a silicon carbide (SiC) semiconductor body having a first surface and a second surface opposite to the first surface. The SiC semiconductor body includes a transistor cell area comprising gate structures, a gate pad area, and an interconnection area electrically coupling a gate electrode of the gate structures and a gate pad of the gate pad area via a gate interconnection. The vertical power semiconductor device further includes a source or emitter electrode. The vertical power semiconductor device further includes a first interlayer dielectric comprising a first interface to the source or emitter electrode and a second interface to at least one of the gate electrode, or the gate interconnection, or the gate pad, and wherein a conduction band offset at the first interface ranges from 1 eV to 2.5 eV.

公开(公告)号：US20210159172A1

公开(公告)日：2021-05-27

申请号：US16697580

申请日：2019-11-27

Applicant: Infineon Technologies AG

Inventor： Thomas BASLER ,  Andreas HUERNER ,  Caspar LEENDERTZ ,  Dethard PETERS

IPC: H01L23/525 ,  H01L23/62 ,  H01L29/16

Abstract: A semiconductor device is provided. In an embodiment, the semiconductor device comprises a control region, a first power region, a second power region, an isolation region and/or a short circuit structure. The control region comprises a control terminal. The first power region comprises a first power terminal. The second power region comprises a second power terminal. The isolation region is between the control region and the first power region. The short circuit structure extends from the first power region, through the isolation region, to the control region. The short circuit structure is configured to form a low-resistive connection between the control region and the first power region during a failure state of the semiconductor device.

公开(公告)号：US20220085601A1

公开(公告)日：2022-03-17

申请号：US17019746

申请日：2020-09-14

Applicant: Infineon Technologies AG

Inventor： Dethard PETERS ,  Thomas BASLER ,  Paul SOCHOR

IPC: H02H9/04 ,  H01L27/06 ,  H01L49/02 ,  H01L29/92 ,  H01L29/16 ,  H01L29/20 ,  H01L29/808 ,  H01L29/78

Abstract: An apparatus includes a unipolar power transistor and an RC snubber. The RC snubber has a capacitor between a poly silicon structure and a semiconductor substrate. The capacitor has a p-n junction. The RC snubber has a resistor between a source of the unipolar power transistor and a first layer forming the capacitor. The unipolar transistor and the RC snubber are coupled in parallel. The RC snubber and the unipolar power transistor are formed monolithically on the semiconductor substrate.

公开(公告)号：US20210273088A1

公开(公告)日：2021-09-02

申请号：US17186281

申请日：2021-02-26

Applicant: Infineon Technologies AG

Inventor： Thomas BASLER ,  Hans-Guenter ECKEL ,  Jan FUHRMANN ,  Dethard PETERS ,  Florian STOERMER

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/40 ,  H01L29/47

Abstract: In an example, a semiconductor device includes an insulated gate transistor cell, a first region (e.g., a drain region and/or a drift region), a cathode region, a second region (e.g., an anode region and/or a separation region), and a source electrode. The insulated gate transistor cell includes a source region and a gate electrode. The source region and the cathode region are in a silicon carbide body. The gate electrode and the cathode region are electrically connected. The cathode region, the source region, and the first region have a first conductivity type. The second region has a second conductivity type and is between the cathode region and the first region. The source electrode and the source region are electrically connected. The source electrode and the second region are in contact with each other. A rectifying junction is electrically coupled between the source electrode and the cathode region.

公开(公告)号：US20200006544A1

公开(公告)日：2020-01-02

申请号：US16454752

申请日：2019-06-27

Applicant: Infineon Technologies AG

Inventor： Ralf SIEMIENIEC ,  Thomas AICHINGER ,  Wolfgang BERGNER ,  Romain ESTEVE ,  Daniel KUECK ,  Dethard PETERS ,  Bernd ZIPPELIUS

IPC: H01L29/78 ,  H01L29/16

Abstract: A semiconductor device includes a silicon carbide body including a transistor cell region and an idle region. The transistor cell region includes transistor cells. The idle region is devoid of transistor cells. The idle region includes a transition region between the transistor cell region and a side surface of the silicon carbide body, a gate pad region, and a diode structure comprising at least one of a merged pin Schottky diode structure or a merged pin heterojunction diode structure in at least one of the transition region or the gate pad region.