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公开(公告)号：US10135452B2
公开(公告)日：2018-11-20
申请号：US15438438
申请日：2017-02-21
Applicant: Infineon Technologies AG , Politecnico Di Milano
Inventor： Dmytro Cherniak , Salvatore Levantino , Marc Tiebout , Roberto Nonis
Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
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公开(公告)号：US11454715B2
公开(公告)日：2022-09-27
申请号：US16705690
申请日：2019-12-06
Applicant: Infineon Technologies AG , POLITECNICO DI MILANO
Inventor： Dmytro Cherniak , Salvatore Levantino , Mario Mercandelli
Abstract: Systems, methods, and circuitries are provided for generating a frequency hopping radar signal. In one example, a radar signal modulator include a frequency offset generator, a phase locked loop, and a bandwidth compensation circuitry. The frequency offset generator is configured to generate a sequence of frequency offsets. The bandwidth compensation circuitry is configured to combine a modulation signal and the sequence of frequency offsets to generate a bandwidth compensated signal. The PLL is configured to receive the bandwidth compensated signal and generate a frequency hopping radar signal based on the bandwidth compensated signal.
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公开(公告)号：US11184013B1
公开(公告)日：2021-11-23
申请号：US17181366
申请日：2021-02-22
Applicant: Infineon Technologies AG
Inventor： Luigi Grimaldi , Giovanni Boi , Dmytro Cherniak , Fabio Padovan
Abstract: A method of operating a phase-locked loop (PLL) having a dynamic element matching (DEM)-driven digitally controlled oscillator (DCO) includes calibrating the PLL, where calibrating the PLL includes opening a loop of the PLL and performing linearity measurements of the DEM-driven DCO when the loop of the PLL is open and when dynamic matching of the DEM-driven DCO is activated, where performing the linearity measurements includes: applying test control words to the DEM-driven DCO to obtain frequencies in a first range of frequencies; and measuring output frequencies of the DEM-driven DCO corresponding to the test control words. Calibrating the PLL further includes calculating calibration information based on the test control words and the measured output frequencies.
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公开(公告)号：US20190081633A1
公开(公告)日：2019-03-14
申请号：US16189949
申请日：2018-11-13
Applicant: Infineon Technologies AG , Politecnico Di Milano
Inventor： Dmytro Cherniak , Salvatore Levantino , Marc Tiebout , Roberto Nonis
CPC classification number: H03L7/24 , H03B5/1212 , H03B5/1215 , H03B5/1228 , H03B5/124 , H03B2201/0208 , H03L7/093 , H03L7/0991 , H03L7/197 , H03L2207/50
Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
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公开(公告)号：US11909405B1
公开(公告)日：2024-02-20
申请号：US18151861
申请日：2023-01-09
Applicant: Infineon Technologies AG
Inventor： Luigi Grimaldi , Thomas Bauernfeind , Dmytro Cherniak , Fabio Versolatto , Andrew Wightwick , Fabio Padovan , Giovanni Boi
Abstract: A digital phase-locked loop (DPLL) circuit includes: a first time-to-digital converter (TDC) and a first digital loop filter (DLF) that are configured to be coupled between a reference clock source and a digitally controlled oscillator (DCO), where the first TDC is configured to, during an acquisition mode, generate a phase error by: receiving a reference clock signal from the reference clock source; receiving a clock signal that is based on an output of the DCO divided by a dividing factor, computing a phase error using the reference clock signal and the clock signal; detecting cycle slipping in the computed phase error; and in response to detecting the cycle slipping, modifying the computed phase error to reduce the impact of cycle slipping on the DPLL circuit; and a first frequency divider circuit configured to generate the clock signal by dividing the output of the DCO by the dividing factor.
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Patent Agency Ranking
公开(公告)号：US11831279B2
公开(公告)日：2023-11-28
申请号：US17227755
申请日：2021-04-12
Applicant: Infineon Technologies AG
Inventor： David Seebacher , Matteo Bassi , Dmytro Cherniak , Fabio Padovan
CPC classification number: H03F1/0205 , H03F3/245 , H03F2200/294 , H03F2200/451
Abstract: In accordance with an embodiment, a method for operating a millimeter-wave power amplifier including an input transistor having an output node coupled to a load path of a cascode transistor includes: receiving a millimeter-wave transmit signal at a control node of the input transistor; amplifying the millimeter-wave transmit signal to form an output signal; providing the output signal to a load coupled to an output node of the cascode transistor; and adjusting a first DC bias current of the input transistor to form a substantially constant second DC bias current of the cascode transistor.
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7.发明授权公开(公告)号：US11716093B2
公开(公告)日：2023-08-01
申请号：US17558704
申请日：2021-12-22
Applicant: Infineon Technologies AG
Inventor： Dmytro Cherniak , Luigi Grimaldi
IPC: H03M3/00
Abstract: A method of applying digital pre-distortion includes: outputting, by a look-up table, a first table value based on an input digital signal; adding the first table value and the input digital signal to generate a first combined signal comprising a first combined value having a first integer coefficient and a first fractional coefficient; separating the first integer coefficient from the first fractional coefficient to generate a first integer signal representing the first integer coefficient and a first fractional signal representing the first fractional coefficient; generating a delta-sigma modulated signal based on the first fractional signal; converting, by a first digital-to-analog, a first digital signal into a first analog signal, wherein the first digital signal is representative of the first integer signal; and converting, by a second DAC, a second digital signal into a second analog signal, wherein the second digital signal is representative of the delta-sigma modulated signal.
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公开(公告)号：US11233520B2
公开(公告)日：2022-01-25
申请号：US17073181
申请日：2020-10-16
Applicant: Infineon Technologies AG , Politecnico Di Milano
Inventor： Dmytro Cherniak , Salvatore Levantino , Marc Tiebout , Roberto Nonis
Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.
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公开(公告)号：US10826508B2
公开(公告)日：2020-11-03
申请号：US16189949
申请日：2018-11-13
Applicant: Infineon Technologies AG , Politecnico Di Milano
Inventor： Dmytro Cherniak , Salvatore Levantino , Marc Tiebout , Roberto Nonis
Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.
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公开(公告)号：US11616509B1
公开(公告)日：2023-03-28
申请号：US17534646
申请日：2021-11-24
Applicant: Infineon Technologies AG
Inventor： Francesco Lombardo , Dmytro Cherniak , Luigi Grimaldi , Nicolo Guarducci
IPC: H03M1/06
Abstract: A dynamic element matching (DEM) encoder is provided that converts an N-bit digital codeword into a pattern of 1-bit values. The DEM encoder includes a binary switching tree that includes plurality of switching blocks interconnected between an encoder input and a plurality of encoder outputs. The plurality of switching blocks are configured to receive a plurality of first control signals such that each switching block receives a respective first control signal and is independently programmable based on the respective first control signal into a first mode or a second mode. Each switching block includes a splitting circuit programmed into the first mode or the second mode to split a digital input into two digital outputs using either both a first splitting operation and a second splitting operation that is different from the first splitting operation or the first splitting operation over the plurality of sampling intervals.
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