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    Space Efficient and Low Parasitic Half Bridge
    1.
    发明申请
    Space Efficient and Low Parasitic Half Bridge 有权

    公开(公告)号：US20210225745A1

    公开(公告)日：2021-07-22

    申请号：US16744967

    申请日：2020-01-16

    Applicant: Infineon Technologies AG

    Inventor： Robert Fehler ,  Eung San Cho ,  Danny Clavette ,  Petteri Palm

    IPC: H01L23/495 ,  H01L25/07 ,  H01L23/00

    Abstract: A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.

    Semiconductor package and passive element with interposer
    2.
    发明授权
    Semiconductor package and passive element with interposer 有权

    公开(公告)号：US11848262B2

    公开(公告)日：2023-12-19

    申请号：US17176678

    申请日：2021-02-16

    Applicant: Infineon Technologies AG

    Inventor： Angela Kessler ,  Robert Carroll ,  Robert Fehler

    IPC: H01L23/498 ,  H01L25/07 ,  H01L21/48 ,  H01L23/00

    CPC classification number: H01L23/49844 ,  H01L21/4853 ,  H01L24/16 ,  H01L25/072 ,  H01L2224/16227 ,  H01L2924/19104

    Abstract: A semiconductor assembly includes an interposer that includes an insulating substrate, a plurality of upper contact pads on an upper surface of the substrate, and a plurality of lower contact pads on a lower surface of the substrate, a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, a first passive electrical element that includes first and second terminals, a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.

    Semiconductor Package and Passive Element with Interposer
    3.
    发明申请
    Semiconductor Package and Passive Element with Interposer 有权

    公开(公告)号：US20220262716A1

    公开(公告)日：2022-08-18

    申请号：US17176678

    申请日：2021-02-16

    Applicant: Infineon Technologies AG

    Inventor： Angela Kessler ,  Robert Carroll ,  Robert Fehler

    IPC: H01L23/498 ,  H01L25/07 ,  H01L23/00 ,  H01L21/48

    Abstract: A semiconductor assembly includes an interposer that includes an insulating substrate, a plurality of upper contact pads on an upper surface of the substrate, and a plurality of lower contact pads on a lower surface of the substrate, a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, a first passive electrical element that includes first and second terminals, a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.

    Semiconductor Package and Passive Element with Interposer
    4.
    发明公开
    Semiconductor Package and Passive Element with Interposer 审中-公开

    公开(公告)号：US20240079310A1

    公开(公告)日：2024-03-07

    申请号：US18389506

    申请日：2023-11-14

    Applicant: Infineon Technologies AG

    Inventor： Angela Kessler ,  Robert Carroll ,  Robert Fehler

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01L25/07

    CPC classification number: H01L23/49844 ,  H01L21/4853 ,  H01L24/16 ,  H01L25/072 ,  H01L2224/16227 ,  H01L2924/19104

    Abstract: A method includes providing an interposer that includes an electrically insulating substrate, upper contact pads disposed on an upper surface, and lower contact pads disposed on a lower surface, providing a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, providing a first passive electrical element that comprises first and second terminals, forming a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, forming a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and forming a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.

    Circuitry and Method of Forming a Circuitry
    5.
    发明申请
    Circuitry and Method of Forming a Circuitry 有权

    公开(公告)号：US20220028840A1

    公开(公告)日：2022-01-27

    申请号：US17384217

    申请日：2021-07-23

    Applicant: Infineon Technologies AG

    Inventor： Robert Fehler ,  Sergey Yuferev

    IPC: H01L25/07 ,  H01L21/56 ,  H01L23/31 ,  H01L23/64 ,  H01L25/18 ,  H01L25/00

    Abstract: A circuitry is provided. The circuitry may include a power stage including a first transistor and a second transistor, an encapsulation including encapsulation material encapsulating the power stage, wherein the first transistor and the second transistor are arranged in an L-shape with respect to each other along their long axes, and a passive electronic component arranged on or embedded within the encapsulation at least partially, in top view, within a rectangular area defined by the L-shape configuration and further next to the first transistor and next to the second transistor.

    Semiconductor package and passive element with interposer
    6.
    发明授权
    Semiconductor package and passive element with interposer 有权

    公开(公告)号：US12131988B2

    公开(公告)日：2024-10-29

    申请号：US18389506

    申请日：2023-11-14

    Applicant: Infineon Technologies AG

    Inventor： Angela Kessler ,  Robert Carroll ,  Robert Fehler

    IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H01L25/07

    CPC classification number: H01L23/49844 ,  H01L21/4853 ,  H01L24/16 ,  H01L25/072 ,  H01L2224/16227 ,  H01L2924/19104

    Abstract: A method includes providing an interposer that includes an electrically insulating substrate, upper contact pads disposed on an upper surface, and lower contact pads disposed on a lower surface, providing a semiconductor package that includes a semiconductor die embedded within a package body and a plurality of package terminals exposed from the package body, providing a first passive electrical element that comprises first and second terminals, forming a first electrical connection between the first terminal of the first passive electrical element and a first one of the lower contact pads via the interposer, forming a second electrical connection between the second terminal of the first passive electrical element and a first one of the package terminals, and forming a third electrical connection between a second one of the package terminals and a second one of the lower contact pads via the interposer.

    Space efficient and low parasitic half bridge
    8.
    发明授权
    Space efficient and low parasitic half bridge 有权

    公开(公告)号：US11469164B2

    公开(公告)日：2022-10-11

    申请号：US16744967

    申请日：2020-01-16

    Applicant: Infineon Technologies AG

    Inventor： Robert Fehler ,  Eung San Cho ,  Danny Clavette ,  Petteri Palm

    IPC: H01L23/48 ,  H01L23/12 ,  H01L23/34 ,  H01L21/00 ,  H05K7/00 ,  H05K1/18 ,  H05K7/10 ,  H05K7/18 ,  H01L23/495 ,  H01L25/07 ,  H01L23/00

    Abstract: A packaged half-bridge circuit includes a carrier having a dielectric core and a first layer of metallization formed on an upper surface of the carrier, first and second semiconductor chips, each including a first terminal, a second terminal, and a control terminal, and a conductive connector mounted on the upper surface of the carrier and electrically connected to the first layer of metallization. The first semiconductor chip is configured as a high-side switch of the half-bridge circuit. The second semiconductor chip is configured as a low-side switch of the half-bridge circuit. At least one of the first and second semiconductor chips is embedded within the dielectric core of the carrier. The conductive connector is electrically connected to one of the first and second terminals from one or both of the first and second semiconductor chips.

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